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HMS81C43XX / gms87c4060 1 november 2001 ver 1.2 HMS81C43XX/gms87c4060 cmos single-chip 8-bit microcontroller for television 1. overview 1.1 description the HMS81C43XX/gms87c4060 is an advanced cmos 8-bit microcontroller with 8~32k(60k) bytes of rom. the device is one of gms800 family. the hynixs HMS81C43XX/gms87c4060 is a powerful microcontroller which provides a high- ly flexible and cost effective solution to many tv applications. the HMS81C43XX/gms87c4060 provides the following standard features: 8~32k(60k) bytes of rom, 256~512/1,536 bytes of ram, 8-bit timer/counter . 1.2 gms87c4060 (otp) features ? 60k bytes on-chip program memory ? 1,536 bytes of on-chip data ram (included 256 bytes stack memory) ? instruction cycle time (ex:nop) - 0.5us at 8mhz ? 40 programmable i/o pins - 33 input/ooutput and 7 output pins ? serial i/o : 8bit x 1ch ?i 2 c bus interface - multimaster (2 pairs interface pins) ? a/d converter : 8bit x 6ch (tbd lsb) ? pulse width modulation - 14bit x 1ch - 8bit x 6ch ?timer - timer/counter : 8bit x 4ch (16bit x 2ch) - basic interval timer : 8bit x 1ch - watch dog timer ? number of interrupt sources : 18 ? on screen display - number of characters : 512 (6 characters are reserved for ic test) - character size : 12 dots(x) x 16 dots(y) - character display size : large, medium, small - display capability : 24characters x 16 lines - character, back ground color : 16kinds - special functions : rounding, outline, sprite, shadow, half tone background,... ? buzzer driving port - 500hz ~ 250khz @8mhz (duty 50%) ? operating range : 4.5v to 5.5v 1.3 HMS81C43XX family features ? on-chip program memry and data memry hms81c4332 ( 32k rom, 512 ram) hms81c4324 ( 24k rom, 256 ram) hms81c4316 ( 16k rom, 256 ram) hms81c4308 ( 8k rom, 256 ram) (included 64/256 bytes stack memory) ? instruction cycle time (ex:nop) - 1.0us at 4mhz ? 21 programmable i/o pins - 19 input/output and 3 output pins ?i 2 c bus interface - multimaster (2 pairs interface pins) device name rom size ram size package HMS81C43XX 8~32k bytes mask rom 256~512 bytes 32 pdip gms87c4060 60k bytes eprom 1,536 bytes 52 sdip
HMS81C43XX / gms87c4060 2 november 2001 ver 1.2 ? a/d converter : 8bit x 6ch (tbd lsb) ? pulse width modulation - 14bit x 1ch - 8bit x 2ch ?timer - timer/counter : 8bit x 4ch (16bit x 2ch) - basic interval timer : 8bit x 1ch - watch dog timer ? number of interrupt sources : 18 ? on screen display - number of characters : 256 - character size : 12 dots(x) x 16 dots(y) - character display size : large, medium, small - display capability : 24characters x 16 lines - character, back ground color : 8 kinds - special functions : rounding, outline, shadow, half tone background... ? buzzer driving port - 250hz ~ 125khz @4mhz (duty 50%) ? operating range : 4.5v to 5.5v ? 1.4 development tools the HMS81C43XX/gms87c4060 is supported by a full- featured macro assembler / linker , osd font editor, an in- circuit emulator choice-dr tm . in circuit emulators choice-dr. (with eva81c4xxx board) assembler / linker hynixs macro assembler / linker font editor ms-windows gui version debugger ms-windows gui version
HMS81C43XX / gms87c4060 3 november 2001 ver 1.2 2. block diagram alu osd (on screen display) controller accumulator interrupt controller data memory osd memory display 8-bit x 4 counter timer/ program memory vector table 8-bit basic timer interval watchdog timer psw system controller timing generator system clock controller reset test xin xout osc1 osc2 r,g,b vdd vss power supply r1 clock generator & index x,y 8bit a/d convertor buzzer r5 pwm 14bit x 1 8bit x 6 data bus i 2 c interface r4 data bus serial i/o interface interrupt interval measure r2 r0 r6 stack pointer pc r00 r01 r02 r03 r04 r05 r06 r07 r67 / int1 r20 / int2 r21 / sclk r22 / sout r23 / sin r24 / int3 r25 / ec2 r26 / int4 r27 / ec3 r40 / pwm0 r41 / pwm1 r42 / pwm2 r43 / pwm3 r44 / scl0 r45 / scl1 / pwm4 r46 / sda0 r47 / sda1 / pwm5 r10 / an0 r11 / an1 r12 / an2 r13 / an3 r14 / an4 r15 / an5 r16 / vd r17 / hd r50 / buzz r51 / pwm8 r52 / int0 r53 r54 / ym r55 / ys r56 / i
HMS81C43XX / gms87c4060 4 november 2001 ver 1.2 3. pin assignment r g b r56 r55/ys r54/ym osc1 osc2 test vdd reset r53 r52/int0 r51/pwm8 r50/buzz r26/int4 r17/hd r16/vd r15/an5 r14/an4 r13/an3 r12/an2 r11/an1 r10/an0 vss xin xout r47/sda1/pwm5 r46/sda0 r45/scl1/pwm4 r44/scl0 r27/ec3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 hynix hms81c4332 r40/pwm0 r41/pwm1 r42/pwm2 r43/pwm3 r44/scl0 r45/scl1/pwm4 r46/sda0 r47/sda1/pwm5 r50/buzz r51/pwm8 r52/int0 r53 vss vdd test osc1 osc2 r54/ym r55/ys r56/i b g r r00 r01 r02 r27/ec3 r26/int4 r25/ec2 r24/int3 r23/sin r22/sout r21/sclk r20/int2 r17/hd r16/vd reset vss xout xin r15/an5 r14/an4 r13/an3 r12/an2 r11/an1 r10/an0 r07 r06 r05 r04 r03 r67/int1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 hynix gms87c4060
HMS81C43XX / gms87c4060 5 november 2001 ver 1.2 4. package diagram 1.665 0.015 0.065 0.1 bsc typ 0.600 bsc 0.550 0 . 0 1 2 0 ~ 15 min 0.015 0.140 0.530 0 . 0 0 8 0.2 max 0.045 0.022 0.120 hynix hms81c4332 1.645 unit: inch
HMS81C43XX / gms87c4060 6 november 2001 ver 1.2 figure 4-1 52pin shrink dip package diagram unit: mm hynix gms87c4060 1 26 27 52 45.97 0.13 0.76 0.13 1.778 0.25 4.38 max. 13.97 0.25 15.24 0.25 0.47 0.13 1.02 0.25 3.81 0.13 3.24 0.20 0.50 min. 0.25 0.05 0 ~ 15
HMS81C43XX / gms87c4060 7 november 2001 ver 1.2 5. pin function v dd : supply voltage. v ss : circuit ground. test : used for shipping inspection of the ic. for normal operation, it should not be connected . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. osc1 : input to the internal on screen display operating circuit. osc2 : output from the inverting osc1 amplifier. r00~r07 : r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r10~r17 : r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r1 serves the functions of the various follow- ing special features. r20~r27 : r2 is a 8-bit cmos bidirectional i/o port. each pins 1 or 0 written to the their port direction register can be used as outputs or inputs. in addition, r2 serves the functions of the various follow- ing special features. r40~r47 : r40~r43 are 8-bit nmos open drain output and r45~r47 are bidirectional cmos input / nmos open drain output port. r4 pins 1 or 0 written to the port direc- tion register can be used as outputs or inputs. in addition, r4 serves the functions of the various follow- ing special features. r50~r56 : r50~r53 are 4-bit cmos bidirectional i/o and r54~r56 are cmos output port. r5 pins 1 or 0 written to the port direction register can be used as outputs or in- puts. in addition, r5 serves the functions of the various follow- ing special features. r67 : r67 is an 1-bit cmos bidirectional i/o port. r67 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r67 serves the functions of the various follow- ing special features. r,g,b : r,g,b cmos output port. each pins controls red, green,. blue color control. port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 an0 (a/d converter input 0) an1 (a/d converter input 1) an2 (a/d converter input 2) an3 (a/d converter input 3) an4 (a/d converter input 4) an5 (a/d converter input 5) vd (vertical sync. input) hd (horisontal sync. input) port pin alternate function r20 r21 r22 r23 r24 r25 r26 r27 int2 (external interrupt input 2) sclk (serial communication clock) sout (serial communication data out) sin (serial communication data in) int3 (external interrupt input 3) ec2 (event counter input 2) int4 (external interrupt input 4) ec3 (event counter input 3) port pin alternate function r40 r41 r42 r43 r44 r45 r46 r47 pwm0 (pulse width modulation output 0) pwm1 (pulse width modulation output 1) pwm2 (pulse width modulation output 2) pwm3 (pulse width modulation output 3) scl0 (i 2 c clock 0) scl1 (i 2 c clock 1) pwm4 (pulse width modulation output 4) sda0 (i 2 c data 0) sda1 (i 2 c data 1) pwm5 (pulse width modulation output 5) port pin alternate function r50 r51 r52 r54 r55 r56 buzz (buzzer output) pwm8 (pulse width modulation output 8) int0 (external interrupt input 0) ym (back ground) ys (edge) i (intencity) port pin alternate function r67 int1 (external interrupt input 1)
HMS81C43XX / gms87c4060 8 november 2001 ver 1.2 pin name pin no. in/out function v dd 39 - supply voltage v ss 12, 40 - circuit ground test 38 i for test purposes. should not be connected. (n.c.) reset 11 i reset signal input x in 14 i main oscillation input x out 13 o main oscillation output osc1 37 i on screen display functions on screen display oscillation input osc2 36 o on screen display osc. output r17/hd 9 i/o horisontal sync. input r16/vd 10 i/o vertical sync. input r 30 o red signal output g 31 o green signal output b 32 o blue signal output r56/i 33 o intencity signal output r55/ys 34 o edge signal output r54/ym 35 o background signal output r40/pwm0 52 o pwm functions 8bit pwm r41/pwm1 51 o 8bit pwm r42/pwm2 50 o 8bit pwm r43/pwm3 49 o 8bit pwm r45/scl1/ pwm4 47 i/o include i 2 c serial clock 1 (scl1) r47/sda1/ pwm5 45 i/o include i 2 c serial data 1 (sda1) r51/pwm8 43 i/o 14bit pwm r44/scl0 48 i/o i 2 c functions i 2 c serial clock 0 r46/sda0 46 i/o i 2 c serial data 0 r23/sin 5 i/o sci functions serial data input r22/sout 6 i/o serial data output r21/sclk 7 i/o serial communication clock r27/ec3 1 i/o timer event functions event counter input 3 r25/ec2 3 i/o event counter input 2 r50/buzzer 44 i/o buzzer function 500hz ~ 250khz @8mhz table 5-1 port function description
HMS81C43XX / gms87c4060 9 november 2001 ver 1.2 r52/int0 42 i/o external interrupt functions external interrupt input 0 r67/int1 26 i/o external interrupt input 1 r20/int2 8 i/o external interrupt input 2 r24/int3 4 i/o external interrupt input 3 r26/int4 2 i/o external interrupt input 4 r10/an0 20 i/o a/d conversion functions analog input 0 r11/an1 19 i/o analog input 1 r12/an2 18 i/o analog input 2 r13/an3 17 i/o analog input 3 r14/an4 16 i/o analog input 4 r15/an5 15 i/o analog input 5 r00 29 i/o digital i/o functions r01 28 i/o r02 27 i/o r03 25 i/o r04 24 i/o r05 23 i/o r06 22 i/o r07 21 i/o r53 41 i/o pin name pin no. in/out function table 5-1 port function description
HMS81C43XX / gms87c4060 10 november 2001 ver 1.2 6. port structures reset test x in , x out osc1, osc2 r00~07, r53 r10~15 (an0~5) reset v dd v ss noise canceler v dd v ss x in x out v ss v dd v ss v dd main frequency clock v ss osdon osc1 osc2 v ss v dd v ss v dd main frequency clock pin data reg. dir. reg. db db db mux rd v dd v ss pin data reg. dir. reg. db db db mux rd v dd v ss an0~5
HMS81C43XX / gms87c4060 11 november 2001 ver 1.2 r16, 17, 20, 24, 25, 26, 27, 52, 67 r21/sclk, r22/sout r23/sin r40~43 (pwm0~3) r44, 45, 46, 47 (scl, sda, pwm) pin data reg. dir. reg. db db db mux rd v dd v ss hd,vd, ec2~3 int0~int4 pin data reg. dir. reg. db db db mux rd v dd v ss sclk mux sout, sclk selection pin data reg. dir. reg. db db db mux rd v dd v ss sin selection pin data reg. db v ss mux pwm0~3 selection pin data reg. dir. reg. db db db mux rd v ss scl, sda mux pwm4,pwm5 selection scl,sda
HMS81C43XX / gms87c4060 12 november 2001 ver 1.2 r50/buzz, r51/pwm8 r54/ym, r55/ys, r56/i r, g, b pin data reg. dir. reg. db db db mux rd v dd v ss mux buzz, pwm8 selection pin data reg. db v dd v ss mux ym, ys, i selection osd on or data reg write. pin r, g, b v dd v ss i osd_on
HMS81C43XX / gms87c4060 13 november 2001 ver 1.2 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +6.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................100 ma maximum current into v dd pin ............................80 ma maximum current sunk by (i ol per i/o pin) ........20 ma maximum output current sourced by (i oh per i/o pin) .................................................................................8 ma maximum current ( s i ol ) ...................................... 80 ma maximum current ( s i oh )...................................... 50 ma note: stresses above those listed under "absolute maxi- mum ratings" may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliab ility. 7.2 recommended operating conditions 7.3 dc electrical characteristics - HMS81C43XX (t a =-10~70 c, v dd =4.5~5.5v) , parameter symbol condition specifications unit min. max. supply voltage v dd f xin =8mhz f osc =16mhz 4.5 5.5 v operating frequency f xin v dd =4.5~5.5v 48mhz on screen display oper- ating frequency f osc v dd =4.5~5.5v 816mhz operating temperature t opr -10 70 c parameter symbol condition specifications unit min. typ. max. high level input voltage v ih1 test , reset , xin, osc1, r17~16, r27~20, r47~44, r52, r67 0.8 v dd - v dd v v ih2 r0, r15~10, r53~50 0.7 v dd - v dd v low level input voltage v il1 test , reset , xin, osc1, r17~16, r27~20, r47~44, r52, r67 0- 0.12 v dd v v il2 r0, r15~10, r53~50 0 - 0.3 v dd v high level output voltage v oh i oh = -5ma r0, r1, r2, r5, r67 v dd - 1 --v i oh = -1.2ma r,g,b v dd - 1 --v low level output voltage v ol i ol = 5ma r0, r1, r2, r4, r5, r67, r, g, b - -1.0v supply current in active mode i dd v dd --30ma
HMS81C43XX / gms87c4060 14 november 2001 ver 1.2 pull-up lekage current i rup v dd = 5.5v, v pin = 0.4v test -1.5 -400 m a high input leakage current i izh v dd = 5.5v , v pin = v dd all input, i/o pins except x in , osc1, r47~40 -5 - 5 m a low input leakage current i izl v dd = 5.5v , v pin = 0v all input, i/o pins except x in , osc1, r47~44 -5 - 5 m a open drain leakage current i loz v dd = 5.5v , v oh = v dd , n-ch tr. off r47~40 --10 m a ram data retention voltage v ram v dd 1.2 - - v i 2 c port impedance (i/o transistor off) r bs v dd = 4.5v , v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v scl0:scl1 (r44:r45) sda0:sda1 (r46:r47) - - 120 w hysterisis vt+ ~ vt- test , reset , xin, osc1, r17~16, r27~20, r47~44, r52, r67 1.0 - - v parameter symbol condition specifications unit min. typ. max.
HMS81C43XX / gms87c4060 15 november 2001 ver 1.2 7.4 a/d comparator characteristics (t a =-10~70 c, v dd =5.0v) 7.5 ac characteristics (t a =-10~70 c, v dd =5v 10% , v ss =0v) parameter symbol pins specifications unit min. typ. max. analog input voltage range v ain an0~an5 v ss - v dd v accuracy n fs --- tbd lsb parameter symbol pins specifications unit min. typ. max. operating frequency f xin x in 4-8mhz f osc osc 8 - 16 mhz external clock pulse width t mcpw x in 62.5 - 125 ns t scpw s clk 0.5 - m s external clock transition time t mrcp, t mfcp x in - - 20 ns t srcp, t sfcp s clk - - 20 ns oscillation stabilizing time t st x in , x out --20ms interrupt pulse width t iw int0~4 2 - - t sys 1 reset input width t rst reset 8- - t sys 1 event counter input pulse width t ecw ec2, ec3 2 - - t sys 1 event counter transition time t rec, t fec ec2, ec3 - - 20 ns 1. t sys is one of 2/f xin main clock operation mode,
HMS81C43XX / gms87c4060 16 november 2001 ver 1.2 figure 7-1 timing chart t mrcp t mfcp x in int0 ~ 4 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset t rec t fec 0.2v dd 0.8v dd ec2, ec3 t iw t iw t rst t ecw t ecw 1/f xin t mcpw t mcpw t srcp t sfcp s clk 0.5v v dd -0.5v 1/f sclk t scpw t scpw
HMS81C43XX / gms87c4060 17 november 2001 ver 1.2 7.6 typical characteristics this data will generate after evaluation. not available at this time.
HMS81C43XX / gms87c4060 18 november 2001 ver 1.2 8. memory organization the gms81c43xx/gms87c4060 has separate address spaces for program memory, data memory and display memory. program memory can only be read, not written to. it can be up to 32k/60k bytes of program memory. data memory can be read and written to up to 256~512/ 1,536 bytes including the stack area. font memory has pre- pared 16k bytes for osd. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 0100 h to 01ff h of the internal data memory. the sp is not initial- ized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. normally, the initial value of "ff h " is used. program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3 . it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a "ya" 16-bit register y a y a caution: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp for 81c4324 (256 ram) ldx #03fh txsp ; sp ? 3f h sp 01 stack address ( 0100 h ~ 013f or 01ff h ) 15 0 87 hardware fixed
HMS81C43XX / gms87c4060 19 november 2001 ver 1.2 after an arithmetic operation and is also changed by the shift instruction or rotate instruction. figure 8-3 psw (program status word) register [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to "0". this flag immedi- ately becomes "0" when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with over- flow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned by dpgr register (address 0f8 h ). it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is addressed by rpr
HMS81C43XX / gms87c4060 20 november 2001 ver 1.2 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01ff sp after execution sp before execution 01fd 01fe 01fd 01fc 01ff push down at acceptance of interrupt pcl pch 01ff 01fc 01fe 01fd 01fc 01ff push down psw at execution of ret instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fd pop up at execution of reti instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fc pop up psw 0100h 01ffh stack depth at execution of push instruction a 01ff 01fe 01fe 01fd 01fc 01ff push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01ff 01ff 01fe 01fd 01fc 01fe pop up pop a (x,y,psw)
HMS81C43XX / gms87c4060 21 november 2001 ver 1.2 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but HMS81C43XX/gms87c4060 has 8~32k/ 60k bytes program memory space only physically imple- mented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5 , shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6 . as shown in figure 8-5 , each area is assigned a fixed lo- cation in program memory. program memory area con- tains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7 . example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffc h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffc h and 0fffd h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area program memory tcall area interrupt vector area 87c4060:1000h feffh ff00h ffc0h ffdfh ffe0h ffffh pcall area 81c4332:8000h ffbfh 81c4324:a000h 81c4316:c000h 81c4308:e000h lda #5 tcall 0fh ; 1byte instruction :; instead of 2 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe i 2 c bus interface interrupt vector area serial i/o interrupt vector area basic interval timer interrupt vector area watchdog timer interrupt vector area timer/counter 3 interrupt vector area timer/counter 1 interrupt vector area v-sync interrupt vector area timer/counter 2 interrupt vector area timer/counter 0 interrupt vector area external interrupt 2 vector area on screen display interrupt vector area external interrupt 0 vector area reset vector area external interrupt 1 vector area 1 frame timer interrupt vector area external interrupt 3/4 vector area "-" means reserved area. note:
HMS81C43XX / gms87c4060 22 november 2001 ver 1.2 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffbf h pcall area (192 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ sub-routine 35 0ff35h 0ff00h 0ffffh upper address is assumed 0ff h. 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh d1 sub-routine 0ffd7h t ? 0d125h reverse
HMS81C43XX / gms87c4060 23 november 2001 ver 1.2 example: the usage software example of vector address and the initialize part in hms81c4324. org 0ffe0h dw i2c ; i2c dw serial ; serial i/o dw bit ; basic interval timer dw watchdog ; watch dog timer dw int3_4 ; interrupt 3/4 dw timer3 ; timer 3 dw timer1 ; timer 1 dw vsync ; vertical sync. dw one_frame ; 1 frame interrupt dw timer2 ; timer 2 dw timer0 ; timer 0 dw int2 ; interrupt 2 dw int1 ; interrupt 1 dw osd ; on screen display dw int0 ; interrupt 0 dw reset ; reset org 0a000h ; start address of 24 kbytes program memory ;******************************************** ; main program * ;******************************************** ; reset: di ; disable all interrupts ldx #0 lda #0 ; ram page0 clear(!0000h->!00bfh) ram_clr: sta {x}+ cmpx #0c0h bne ram_clr ; call osd_stop ; stop osd display ; ldx #03fh ; stack pointer initialize txsp ldm r0, #0 ; normal port 0 ldm r0dd,#1000_0010b ; normal port direction : : : :
HMS81C43XX / gms87c4060 24 november 2001 ver 1.2 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into four groups, a user ram, control registers, stack, and osd memory. figure 8-8 data memory map user memory the gms87c4060 has 1,536 8 bits for the user memory (ram). hms81c4332 has 512 x 8 bit for the user mem- ory (ram) addressed 000h ~ 23fh except peripheral reg. (64 bytes) . hms81c4308/16/24 has 256 x 8 bit ram ad- dressed 000h ~ 13fh except peripheral register (0c0h~0ffh) control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the basic control registers are in address range of 00c0 h to 00ff h . and osd control registers are assigned within 0ae0 h ~ 0aff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction. example; to write at ckctlr ldm clctlr,#09h ;divide ratio ? 8 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 20. page0 ram (192 bytes) peripheral reg. (64 bytes) 0100h 00c0h 0000h ram (256 bytes) 0200h ram (256 bytes) 0300h ram (256 bytes) 0400h ram (256 bytes) 0500h ram (256 bytes) 0600h ram (64 bytes) 0a00h osd ram (192 bytes) 0ae0h peripheral reg. (32 bytes) 0c00h sprite ram (96 bytes) empty area page1 page2 page3 page4 page5 page6 pagea pagec 063fh stack area 0c5fh address symbol r/w reset value addressing mode 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh r0 r0dd r1 r1dd r2 r2dd r4 r4dd r5 r5dd r6 r6dd func1 func2 r/w w r/w w r/w w r/w w r/w w r/w w w w ???????? 00000000 ???????? 00000000 ???????? 00000000 ???????? 0000---- ???????? ----0000 ?------- 0------- -0000000 ---00000 byte, bit 1 byte 2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte table 8-1control registers
HMS81C43XX / gms87c4060 25 november 2001 ver 1.2 0d0h 0d1h 0d2h 0d3h 0d4h 0d5h 0d6h 0d7h 0d8h 0d9h 0dah 0dbh 0dch 0deh 0dfh tm0 tm2 tdr0 tdr1 tdr2 tdr3 bitr ckctlr wdtr icar icdr icsr iccr1 iccr2 siom sior r/w r/w r/w r/w r/w r/w r w w r/w r/w r/w r/w r/w r/w r/w -0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 0001000- 00000000 00000000 -0000001 ???????? byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit 0e0h 0e1h 0e2h 0e3h 0e4h 0e5h 0e8h 0e9h 0eah 0ebh 0eeh 0efh pwmr0 pwmr1 pwmr2 pwmr3 pwmr4 pwmr5 pwm8h pwm8l pwmcr1 pwmcr2 bur aips w w w w w w r/w r/w r/w r/w w w ???????? ???????? ???????? ???????? ???????? ???????? ???????? --?????? 00000000 --0-0000 ???????? --000000 byte byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte 0f0h 0f1h 0f2h 0f3h 0f4h 0f5h 0f6h 0f7h 0f9h 0fah 0fbh 0fch 0fdh adcm adr ieds imod ienl irql ienh irqh idcr idfs idr dpgr tmr r/w r w r/w r/w r/w r/w r/w r/w r r r/w w --011101 ???????? --000000 --000000 0000000- 0000000- 00000000 00000000 0000-000 1----001 ???????? ----0000 ???????? byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte 0ae0h 0ae1h 0ae2h 0ae3h 0ae4h 0ae5h 0ae6h 0ae8h 0ae9h 0af0h 0af1h 0af3h 0af4h osdcon1 osdcon2 osdpol fdwset edgecol osdln lhpos spvpos sphpos l1attr l1vpos l2attr l2vpos r/w r/w w w w r w w w w w w w 00000000 -0000000 ???????? 01111010 10000111 ---00000 ???????? ???????? ???????? ???????? ???????? ???????? ???????? byte, bit byte, bit byte byte byte byte byte byte byte byte byte byte byte table 8-1control registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clear- ing bit.
HMS81C43XX / gms87c4060 26 november 2001 ver 1.2 8.4 addressing mode the gms800 series uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: fe10: 0435 adc #35h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit direct page accessable register (dpgr) and 8-bit immediate data. example: g=1, dpgr=0ch f100: e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 e551: c535 lda 35h;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data , i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; f100: 0735f0 adc!0f035h ;a ? rom[0f035h] 35 a+35h+c ? a 04 memory 0fe10 h e4 0f100 h data ? 55h ~ ~ ~ ~ data 0c35 h t 35 0f102 h 55 0f101 h a data 35 35 h 0e551 h data ? a t ~ ~ ~ ~ c5 0e550 h 07 0f100 h ~ ~ ~ ~ data 0f035 h p f0 0f102 h 35 0f101 h a a+data+c ? a address: 0f035
HMS81C43XX / gms87c4060 27 november 2001 ver 1.2 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag and dpgr. f100: 983501 inc!0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1, dpgr=03 h e550: d4 lda {x};acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h f100: db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h e550: c645 lda 45h+x 98 0f100 h ~ ~ ~ ~ data 135 h t 01 0f102 h 35 0f101 h data+1 ? data ? address: 0135 data d4 315 h 0e550 h data ? a t ~ ~ ~ ~ data db 35 h data ? a t ~ ~ ~ ~ 36h ? x 0f100 h data 45 3a h 0e551 h data ? a t ~ ~ ~ ~ c6 0e550 h 45h+0f5h=13ah ?
HMS81C43XX / gms87c4060 28 november 2001 ver 1.2 y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h f100: d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 fa00: 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h fa00: 1625 adc [25h+x] d5 0f100 h data ? a t ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h ? fa 0f102 h 00 0f101 h 0a 35 h jump to address 0e30a h t ~ ~ ~ ~ 35 0fa00 h e3 36 h 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ ? a + data + c ? a 25 + x(10) = 35 h t
HMS81C43XX / gms87c4060 29 november 2001 ver 1.2 y indexed indirect ? ? ? ? [dp]+y processes momory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h fa00: 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 fa00: 1f25e0 jmp [!0c025h] 05 25 h 0e005 h + y(10) = 0e015 h t ~ ~ ~ ~ 25 0fa00 h e0 26 h 17 0e015 h data ~ ~ ~ ~ ? a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h 25 0e725 h next ~ ~ ~ ~ 1f program memory t address 0e30a h
HMS81C43XX / gms87c4060 30 november 2001 ver 1.2 9. i/o ports the gms87c4060 has digital ports (r0, r1, r2, r4, r5 and r6) and osd ports (r,g,b), but HMS81C43XX has r1, r2, r4, r5 and osd ports (r,g,b) these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in gen- eral, in a initial reset state, r ports are used as a general purpose digital port. 9.1 registers for port port data registers the port data registers in i/o buffer in each r ports are represented as a type d flip-flop, which will clock in a val- ue from the internal bus in response to a "write to data reg- ister" signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a "read data reg- ister" signal from the cpu. the level of the port pin itself is placed on the internal bus in response to "read data reg- ister" signal from the cpu. some instructions that read a port activating the "read register" signal, and others acti- vating the "read pin" signal port direction registers all pins have data direction registers which can define these ports as output or input. a "1" in the port direction register configure the corresponding port pin as output. conversely, write "0" to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write "55 h " to address 0c1 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1 . all the port direction registers in the HMS81C43XX/ gms87c4060 have 0 written to them by reset function. on the other hand, its initial status is input. figure 9-1 example of port i/o assignment i : input port write "55 h " to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r4 data r0 direction r4 direction 0c0h 0c1h 0c8h 0c9h 76543210 bit 76543210 port o : output port ~ ~ ~ ~
HMS81C43XX / gms87c4060 31 november 2001 ver 1.2 9.2 i/o ports configuration r0 ports r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c1 h ). the control registers for r0 are shown below. in addition, port r0 is only digital i/o. after reset, r0dd value is "0", r0 acts as normal digital input port. r1 ports r1 is an 8-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c3 h ). r1 port have secondary functions as following table. the control registers for r1 are shown below. port r1 is multiplexed with various special features.the control registers controls the selection of alternate func- tion. after reset, r1 port acts as normal digital input port. the way to select alternate function such as a/d input or hd,vd will be shown in each peripheral section. port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 an0 (a/d input 0) an1 (a/d input 1) an2 (a/d input 2) an3 (a/d input 3) an4 (a/d input 4) an5 (a/d input 5) vd (vertical sync. input) hd (horizontal sync. input) r0 data register r0 address : 00c0 h reset value : undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0dd address : 00c1 h reset value : 0000 0000 b 0: input 1: output rw rw rw rw rw rw rw rw www w wwww r1 data register r1 address : 00c2 h reset value : undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r1 direction register r1dd address : 00c3 h reset value : 0000 0000 b 0: input 1: output a/d convertor mode register adcm address : 00f0 h reset value : --01 1101 b port property analog input pin selector register aips address : 00ef h reset value : --00 0000 b 0: digital i/o 1: analog input r16/vd select port function select register 2 func2 address : 00cf h reset value : ---0 0000 b 0: r16 i/o 1: vd input aden ads2 ads1 ads0 adst adsf hds vds yms yss is a/d status 0: busy 1: finish a/d start 0: ignore 1: a/d start a/d port select 000: an0 001: an1 a/d enable 0: disable 1: enable 010: an2 011: an3 100: an4 101: an5 110: an6 111: no analog port r17/hd select 0: r17 i/o 1: hd input rw rw rw rw rw rw rw rw rw rw rw rw rw r wwwwwwww wwwwww wwwww
HMS81C43XX / gms87c4060 32 november 2001 ver 1.2 r2 port r2 is an 8-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 00c5 h ). the control registers for r2 are shown below. r4 port r4 is consrutced with 4-bit open drain output port and 4- bit cmos bidirectional i/o port (address 0c8 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0c9 h ). the control registers for r4 are shown below. r2 data register r2 address : 00c4 h reset value : undefined r27 r26 r25 r24 r23 r22 r21 r20 port direction r2 direction register r2dd address : 00c5 h reset value : 0000 0000 b 0: input 1: output serial i/o mode register siom address : 00de h reset value : -000 0001 b 00: ignore edge ext. interrupt edge selection register ieds address : 00f2 h reset value : --00 0000 b 01: falling edge 10: rising edge r20/int2 port function select register 1 func1 address : 00ce h reset value : -000 0000 b 0: r20 1: int2 sm1 sm0 sck1 sck0 siost siosf int4s int3s int2s int1s int0s seriial status 0: busy 1: finish serial start 0: ignore 1: serial start clock select 00: ps3 01: ps4 serial i/o 0: serial in 1: serial out 10: ps5 11: external iosw ec2s ec3s sm1 0 0 1 1 sm0 0 1 0 1 mode - send receive - r21 r21 sclk sclk r21 r22 r22 sout r22 r22 r23 r23 r23 sin r23 r24/int3 0: r24 1: int3 r26/int4 0: r26 1: int4 r27/ec3 0: r27 1: ec3 r25/ec2 0: r25 1: ec2 ied2h ied2l ied1h ied1l ied0h ied0l 11: falling/rising edge int2 rw rw rw rw rw rw rw rw wwwwwwww rw rw rw rw rw rw r wwwwwww wwwwww r4 data register r4 address : 00c8 h reset value : undefined r47 r46 r45 r44 r43 r42 r41 r40 port direction r4 direction register r4dd address : 00c9 h reset value : 0000 ---- b 0: input 1: output i 2 c control register 1 iccr1 address : 00db h reset value : 00-0 0000 b en5,4,3,2,1 : r47,45,43,42,41,40 pwm control register 1 pwmcr1 address : 00ea h reset value : 0000 0000 b 0: r4x acts normal digital port 1: r4x acts pwm output port als eso bc2 bc1 bc0 en2 en1 en0 en8 cnt bit count 000 b (8bit) i 2 c enable 0: disable 1: enable bsw0 en3 en4 en5 bsw1 0 0 1 1 bsw0 0 1 0 1 r44 r44 scl0 r44 scl r45 r45/pwm4 r45/pwm4 scl1 scl r46 r46 sda0 r46 sda bsw1 001 b ~111 b (1~7bit) r47 r47/pwm5 r47/pwm5 sda1 sda slave address identification 0: accept (addressing format) 1: decline (free data format) rw rw rw rw rw rw rw rw wwwwwwww rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14/8bit pwm count 0: count start 1: count stop r51/pwm8 select 0: r51 1: pwm8
HMS81C43XX / gms87c4060 33 november 2001 ver 1.2 r5 port r5 is an 7-bit port (address 0ca h ). each i/o pin can inde- pendently used as an input or an output through the r5dd register (address 0cb h ). the control registers for r5 are shown below r6 port r6 is an 1-bit cmos bidirectional i/o port (address 0cc h ). each i/o pin can independently used as an input or an output through the r6dd register (address 0cd h ). the control registers for r6 are shown below r5 data register r5 address : 00ca h reset value : undefined r56 r55 r54 r53 r52 r51 r50 port direction r5 direction register r5dd address : 00cb h reset value : ---- 0000 b 0: input 1: output 00: ignore edge ext. interrupt edge selection register ieds address : 00f2 h reset value : --00 0000 b 01: falling edge 10: rising edge r52/int0 port function select register 1 func1 address : 00ce h reset value : -000 0000 b 0: r52 1: int0 int4s int3s int2s int1s int0s ec2s ec3s ied2h ied2l ied1h ied1l ied0h ied0l 11: falling/rising edge r56/i port function select register 2 func2 address : 00cf h reset value : ---0 0000 b 0: r56 1: i output hds vds yms yss is r55/ys 0: r55 1: ys output r54/ym 0: r56 1: ym output pwm control register 2 pwmcr2 address : 00eb h reset value : --0- 0000 b pol2 pol1 en7 en6 buzs int2 r50/buzz 0: r50 1: buzz rw rw rw rw rw rw rw wwww wwwwwww wwwww rw rw rw rw rw wwwwww r6 data register r6 address : 00cc h reset value : undefined port direction r6 direction register r6dd address : 00cd h reset value : 0--- ---- b 0: input 1: output 00: ignore edge ext. interrupt edge selection register ieds address : 00f2 h reset value : --00 0000 b 01: falling edge 10: rising edge r67/int1 port function select register 1 func1 address : 00ce h reset value : -000 0000 b 0: r67 1: int1 int4s in t3s int2s int1s in t0s ec2s ec3s ied2h ied2l ied1h ied1l ied0h ied0l 11: falling/rising edge int1 rw www wwww wwwwww r67 w
HMS81C43XX / gms87c4060 34 november 2001 ver 1.2 10. clock generator as shown in figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and the peripheral hardware. it con- tains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. the system clock can also be obtained from the external oscillator. the clock generator produces the system clocks forming clock pulse, which are supplied to the cpu and the periph- eral hardware. to the peripheral block, the clock among the not-divided original clocks, divided by 2 , 4,..., up to 1024 can be pro- vided. peripheral clock is enabled or disabled by bit 4 of the peripheral clock enable register (enpck). figure 10-1 block diagram of clock generator note: on the initial reset, all peripherals are run because peripheral clock is supplied to each function block. if you want to see more details, see clock control register (ckctlr). main clock minimum instruction cycle time (ex:nop ; f ex 4clock is needed) 3.6mhz 1,111ns 4mhz 1,000ns 8mhz 500ns internal system clock prescaler enpck ? 1 peripheral clock f ex clock control register [0d6 h ] ckctlr wdt enpck btcl bts2 bts1 bts0 clock pulse generator on osc circuit ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ? 2 ? 4 ? 8 ? 16 ? 32 ? 64 ? 128 ? 256 ? 512 ? 1024 ? 2048 test mode register address : 00fd h reset value : 0000 0000 b tmr wwwwww ww 0000 0110b normal operation mode clock control register address : 00d6 h reset value : --01 0111 b ckctlr wdt enpck btcl bts2 bts1 bts0 on peri. clock 0: stop 1: supply watch-dog timer select 0: normal 6bit timer 1: watch-dog timer b.i.t set 0: free run 1: b.i.t clear b.i.t clock wwwwww
HMS81C43XX / gms87c4060 35 november 2001 ver 1.2 11. timer 11.1 basic interval timer the HMS81C43XX/gms87c4060 has one 8-bit basic in- terval timer that is free-run and can not be stopped. block diagram is shown in figure 11-1 . the basic interval timer generates the time base for watchdog timer counting, and etc. it also provides a basic interval timer interrupt (bitif). as the count overflow from ff h to 00 h , this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 11-2 . source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and ad- dress 00d6 h is read as a bitr and written to ckctlr.. figure 11-1 block diagram of basic interval timer table 11-1 basic interval timer interrupt time mux basic interval timer interrupt bitr select input clock 3 source clock 8-bit up-counter bitck btcl f ex ? 2 10 f ex ? 2 9 f ex ? 2 8 f ex ? 2 7 f ex ? 2 6 f ex ? 2 5 f ex ? 2 4 watchdog timer clock (wdtck) clear overflow internal bus line [0d6 h ] [0d6 h ] bitif clock control register ckctlr wdt enpck btcl bts2 bts1 bts0 on ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 f ex ? 2 11 bts2~0 source clock interrupt (overflow) period pre-scaler output at f ex =8mhz 000 001 010 011 100 101 110 111 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 f ex ? 2 4 f ex ? 2 5 f ex ? 2 6 f ex ? 2 7 f ex ? 2 8 f ex ? 2 9 f ex ? 2 10 f ex ? 2 11 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 ms
HMS81C43XX / gms87c4060 36 november 2001 ver 1.2 figure 11-2 bitr: basic interval timer mode register 11.2 timer 0, 1 timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, control register, and comparator as shown in figure 11-3 . these timers can run separated 8bit timer or combined 16bit timer. these timers are operated by internal clock. the contents of tdr1 are compared with the contents of up-counter t1. if a match is found, a timer/counter 1 inter- rupt (t1if) is generated, and the counter is cleared. count- ing up is resumed after the counter is cleared. note: you can read timer 0, timer 1 value from tdr0 or tdr1. but if you write data to tdr0 or tdr1, it changes timer 0 or timer 1 modulo data, not timer value. the content of tdr0, tdr1 must be initialized (by soft- ware) with the value between 01 h and ff h ,not to 00 h . or not, timer 0 or timer 1 can not count up forever. the control registers for timer 0,1 are shown below. ckctlr initial value: undefined address: 00d6 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution : 8-bit binary counter address : 00d6 h reset value : --01 0111 b wdt enpck btcl bts2 bts1 bts0 on peri. clock 0: stop 1: supply watch-dog timer select 0: normal 6bit timer 1: watch-dog timer b.i.t set 0: free run 1: clear 8-bit counter (bitr) to "0". this bit becomes 0 b.i.t clock automatically after 1 machine cycle wwwwww rrrrrrrr timer mode register 0 tm0 address : 00d0 h reset value : -000 0000 b timer 0 data register tdr0 address : 00d2 h reset value : undefined t1sl0 t0st t0cn t0sl1 t0sl0 t1sl1 t1st timer 1 data register tdr1 address : 00d3 h reset value : undefined timer 0 input clock 00: ps2 (f ex / 2 2 ) 01: ps4 (f ex / 2 4 ) 10: ps6 (f ex / 2 6 ) 11: ps8 (f ex / 2 8 ) timer 1 input clock 00: timer 0 overflow (16bit mode) 01: ps2 (f ex / 2 2 ) 10: ps4 (f ex / 2 4 ) 11: ps6 (f ex / 2 6 ) 0: count hold 1: count continue timer 0 control 0: count hold 1: count clear and start timer 0 start 0: count hold 1: count clear and start timer 1 start rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
HMS81C43XX / gms87c4060 37 november 2001 ver 1.2 . figure 11-3 simplified block diagram of 8bit timer0, 1 figure 11-4 count example of timer 8bit comparator internal bus line tm0 tdr0 timer 0 t0if clock tdr1 timer 1 clock clear clear 8bit comparator t1if mux ps2 ps4 ps6 ps8 mux nc ps2 ps4 ps6 t0cn t0st t1st timer 0 (t0if) interrupt tdr0 time occur interrupt occur interrupt stop clear & start disable enable start & stop t0st t0cn control count u p-c o u nt ~ ~ ~ ~ t0st = 0 t0st = 1 t0cn = 0 t0cn = 1
HMS81C43XX / gms87c4060 38 november 2001 ver 1.2 figure 11-5 simplified block diagram of 16bit timer0, 1 11.3 timer / event counter 2, 3 timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, control register, and comparator as shown in figure 11-5 . these timers have two operating modes. one is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin r25/ec2, r27/ec3. these timers can run separated 8bit timer or combined 16bit timer. note: you can read timer 2, timer 3 value from tdr2 or tdr3. but if you write data to tdr2 or tdr3, it changes timer 2 or timer 3 modulo data, not timer value. the content of tdr2, tdr3 must be initialized (by soft- ware) with the value between 01 h and ff h ,not to 00 h . or not, timer 2 or timer 3 can not count up forever. the control registers for timer 2,3 are shown below internal bus line tm0 tdr0 timer 0 clock tdr1 timer 1 clock clear clear 16bit comparator t1if mux ps2 ps4 ps6 ps8 t0cn t0st 00 timer mode register 2 tm2 address : 00d1 h reset value : -000 0000 b timer 2 data register tdr2 address : 00d4 h reset value : undefined t3sl0 t2st t2cn t2sl1 t2sl0 t3sl1 t3st timer 3 data register tdr3 address : 00d5 h reset value : undefined timer 2 input clock 00: ps2 (f ex / 2 2 ) 01: ps4 (f ex / 2 4 ) 10: ps6 (f ex / 2 6 ) 11: ps8 (f ex / 2 8 ) timer 3 input clock 00: timer 2 overflow (16bit mode) 01: ps2 (f ex / 2 2 ) 10: ps4 (f ex / 2 4 ) 11: ps6 (f ex / 2 6 ) 0: count hold 1: count continue timer 2 control 0: count hold 1: count clear and start timer 2 start 0: count hold 1: count clear and start timer 3 start port function select register 1 func1 address : 00ce h reset value : -000 0000 b int4s int3s int2s int1s int0s ec2s ec3s r27/ec3 0: r27 1: ec3 r25/ec2 0: r25 1: ec2 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw wwww www
HMS81C43XX / gms87c4060 39 november 2001 ver 1.2 . figure 11-6 simplified block diagram of 8bit timer/event counter 2,3 figure 11-7 count example of timer / event counter 8bit comparator internal bus line tm2 tdr2 timer 2 t2if clock tdr3 timer 3 clock clear clear 8bit comparator t3if mux ec2 ps2 ps4 ps6 mux nc ec3 ps2 ps4 t2cn t2st t3st timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt stop clear & start disable enable start & stop t2st t2cn control count u p-c o u nt ~ ~ ~ ~ t2st = 0 t2st = 1 t2cn = 0 t2cn = 1
HMS81C43XX / gms87c4060 40 november 2001 ver 1.2 figure 11-8 simplified block diagram of 16bit timer/event counter 2,3 timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock in- put. the contents of tdrn (n=0~3) are compared with the contents of up-counter, timer n. if match is found, a timer n interrupt (tnif) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdrn is changeable by software, time in- terval is set as you want figure 11-9 timer mode timing chart event counter mode in event timer mode, counting up is started by an external trigger. this trigger means falling edge of the ecn (n=2~3) pin input. source clock is used as an internal clock selected with tm2. the contents of tdrn are compared with the contents of the up-counter. if a match is found, an tnif in- terrupt is generated, and the counter is cleared to 00 h . the counter is restarted by the falling edge of the ecn pin in- put. the maximum frequency applied to the ecn pin is f ex /2 [hz] in main clock mode. in order to use event counter function, the bit ec2s, ec3 of the port function select register1 func1(address 0ce h ) is required to be set to "1". after reset, the value of tdrn is undefined, it should be internal bus line tm2 tdr2 timer 2 clock tdr3 timer 3 clock clear clear 16bit comparator t3if mux ec2 ps4 ps6 ps8 t0cn t0st 00 0 n-2 2 0 n 3 n-1 n ~ ~ ~ ~ ~ ~ source clock up-counter tdrn (n=0~3) tnif (n=0~3) interrupt start count ~ ~ 12 3 ~ ~ ~ ~ 1 4 match detect counter clear
HMS81C43XX / gms87c4060 41 november 2001 ver 1.2 initialized to between 01 h ~ff h not to 00 h figure 11-10 event counter mode timing chart the interval period of timer is calculated as below equa- tion. figure 11-11 count example of timer / event counter 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ecn (n=2~3) pin up-counter tdrn (n=2~3) tnif (n=2~3) interrupt start count ------- -
= ~ ~ timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt occur interrupt interrupt period u p -coun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 n n-1 p cp = p cp x n n-2 tdr2=n
HMS81C43XX / gms87c4060 42 november 2001 ver 1.2 figure 11-12 count operation of timer / event counter timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt stop clear & start disable enable start & stop t2st t2cn control count up-coun t ~ ~ ~ ~ t2st = 0 t2st = 1 t2cn = 0 t2cn = 1
HMS81C43XX / gms87c4060 43 november 2001 ver 1.2 12. a/d converter the a/d convertor circuit is shown in figure 12-1 . the a/d convertor circuit consists of the comparator and control register aips(00ef h ), adcm(00f0 h ), adr(00f1 h ). the aips register select normal port or an- alog input. the adcm register control a/d converters activity. the adr register stores a/d converted 8bit re- sult. the more details are shown figure 12-2 . figure 12-1 block diagram of a/d convertor circuit control the HMS81C43XX/gms87c4060 contains a a/d con- verter module which has six analog inputs. 1. first of all, you have to select analog input pin by set the adcm and aips. 2. set aden (a/d enable bit : adcm bit5). 3. set adst (a/d start bit : adcm bit1). we recommend you do not set aden and adst at once, it makes worse a/d converted result. 4. adst bit will be cleared automatically 1cycle after you set this. example: : ; set aips, change ? to what you want ; 0 : digital port ; 1 : analog port ldm aips,#00??????b ; set aden, xxx is analog port number ldm adcm,#001xxx00b ; or set1 aden ; set adst, xxx is analog port number ldm adcm,#001xxx10b ; or set1 adst : : 5. after a/d conversion is completed, adsf bit and inter- rupt flag ifa will be set. (a/d conversion takes 36 ma- chine cycle : 9us when f ex =8mhz). note: make sure aips bits, if you using a port which is set digital input by aips, analog voltage will be flow into mcu internal logic not a/d converter. sometimes device or port is damaged permanently. comparator an0 mux an1 an2 an3 port select + - s/h adcm [f0 h ] aden ads2 ads1 ads0 adst adsf adr [f1 h ] an4 an5 control circuit register ladder succesive approximation circuit ifa vref
HMS81C43XX / gms87c4060 44 november 2001 ver 1.2 figure 12-2 a/d convertor registers a/d result register adr address : 00f1 h reset value : undefined a/d convertor mode register adcm address : 00f0 h reset value : --01 1101 b port property analog input pin selector register aips address : 00ef h reset value : --00 0000 b 0: digital i/o 1: analog input aden ads2 ads1 ads0 adst adsf a/d status 0: busy 1: finish a/d start 0: ignore 1: a/d start a/d port select 000: an0 001: an1 a/d enable 0: disable 1: enable 010: an2 011: an3 100: an4 101: an5 11x: no analog port 8bit result is stored rw rw rw rw rw r rrrrrrrr wwwwww
HMS81C43XX / gms87c4060 45 november 2001 ver 1.2 13. serial i/o the serial i/o circuit is shown in figure 13-1 . the serial i/o circuit consists of the octal counter, si- or(df h ), siom(de h ). the sior register stores received data or data which will be transfered. the siom register controls serial communication mode, speed, start, etc. the more details about registers are shown figure 13-2 . figure 13-1 block diagram of serial i/o circuit control the HMS81C43XX/gms87c4060 contains a synchronous type serial i/o module. 1. you have to select serial i/o pins by set the sm1~0. note: sout pin can handle serial data output or serial data input. you can input serial data to sout pin when iosw bit is 1. but sin pin is dedicated serial data input pin. 2. you have to select serial communication clock by set the sck1~0. 3. if you want to send data, write it to sior. or not skip this. 4. start serial communication by set siost(serial i/o start, siom bit1). 5 . after serial communication is completed, siosf bit and interrupt flag ifsio will be set. mux siom [de h ] sm1 sm0 sck1 sck0 siost siosf sior [df h ] sout sin octal counter control circuit ifsio iosw 1 0 mux ps3 ps5 ps4 exclk sclk d7 d6 d5 d4 d3 d2 d1 d0 sm1 sm0 function port select r21 r22 r23 00 - r21r22r23 0 1 send sclk sout r23 10 receive sclkr22sin 11 - r21r22r23 sck1 sck0 selected clock ex: frequency (f ex =8mhz) 0 0 ps3 1us 0 1 ps4 2us 1 0 ps5 4us 1 1 external clock user define
HMS81C43XX / gms87c4060 46 november 2001 ver 1.2 figure 13-2 serial i/o registers figure 13-3 example for serial i/o check by s/w figure 13-4 serial i/o timing chart serial i/o data register sior address : 0df h reset value : undefined serial i/o mode register siom address : 0de h reset value : -000 0001 b serial status 0: busy 1: finish serial comm. start 0: ignore 1: comm. start input select 0: sin 1: sout sm1 sm0 sck1 sck0 siost siosf iosw clock select send / receive d7 d6 d5 d4 d3 d2 d1 d0 rw rw rw rw rw rw r rw rw rw rw rw rw rw rw serial i/o interrupt service routine siosf=1? se=0 // se : interrupt enable bit abnormal operation write siom sr=0? // sr : interrupt request flag normal operation overrun error no yes no yes d0 input clock sout sin ifsio sclk siost d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7
HMS81C43XX / gms87c4060 47 november 2001 ver 1.2 14. pulse width modulation (pwm) the pwm circuit is shown in figure 14-1 , figure . the pwm circuit consists of the counter, comparator, data register. the pwm control registers are pwmr7~0, pwmcr2~1, pwm8h, pwm8l. the more details about registers are shown figure 14-2 . figure 14-1 8bit register (pwm7~0) circuit figure 14-2 14bit register (pwm8) circuit example (f ex =8mhz) 14bit pwm 8bit pwm resolution 0.5us 4us input clock 2mhz 250khz frame cycle 8,192us 1,024us pwmcr2 [eb h ] 8bit counter pwm0 pwmcr1 [ea h ] 8bit comparator pwmr0 [e0 h ] en5 en4 en3 en2 en1 en0 pwmr1 [e1 h ] pwmr2 [e2 h ] pwmr3 [e3 h ] pwmr4 [e4 h ] pwmr5 [e5 h ] pwm5 pwm4 pwm3 pwm2 pwm1 if1frame ps5 cntb pwmcr2 [eb h ] 14bit counter pwm8 pwmcr1 [ea h ] 14bit comparator pwmr8h 8bit [e8 h ] en8 ps2 cntb pwmr8l 6bit [e9 h ] msb lsb internal control
HMS81C43XX / gms87c4060 48 november 2001 ver 1.2 8bit pwm control the HMS81C43XX/gms87c4060 contains a one 14bit pwm and six 8bit pwm module. 1. 8bit pwm0~5 is wholy same internal circuit, but pwm0~5 output port is nmos open drain. 2. al l pwm polarity has the same by pol2s value. 3. calulate frame cycle and pulse width is as following. pwm frame cycle = 2 13 / f ex (sec) pwm width = (pwmrn+1) * 2 5 / f ex (n=0~5) pulse duty (%) = (pwmrn +1) / 256 *100(%) (n=0~5) figure 14-3 wave form example for 8bit pwm 4. pwm output is enabled during enn(n=0~5) bit (see pwmcr1~2) contains 1. figure 14-4 8bit pwm registers 5. cntb controls all pwm counter enable. if cntb=0, counter is enabled. 14bit pwm control 1. 14bit pwms operation concept is not the same as 8bit pwm. 1 pwm frame contains 64 sub pwms. pwm8h : set sub pwms basic pulse width. pwm8l : number of sub pwm which is added 1 clock. 2. pwm polarity is selected by pol1s value. if pol1=0, positive polarity. 3. calulate frame cycle and pulse width is as following. main pwm frame cycle = 2 16 / f ex (sec). sub pwm frame cycle = main frame cycle / 64. 4. table 14-1, pwm8l and sub frame matching table, on page 48 show pwm8l function. figure 14-5 wave form example for 14bit pwm positive polarity (pol2=0) 1 2 negative polarity (pol2=1) 1 2 1. frame cycle 2. pulse width pwm data register pwmr0~5 address : 0e0~e5 h reset value : undefined d7 d6 d5 d4 d3 d2 d1 d0 en5,4,3,2,1 : r47,45,43,42,41,40 pwm control register 1 pwmcr1 address : 0ea h reset value : 0000 0000 b 0: r4x acts normal digital port 1: r4x acts pwm output port en2 en1 en0 en8 cntb en3 en4 en5 pwm control register 2 pwmcr2 address : 0eb h reset value : --0- 00-- b pol2 pol1 buzs 8bit pwm polarity 0: positive (pwm from rising edge) 1: negative (pwm from rising edge) 14bit counter enable 0: counter run 1: counter stop wwwwwwww rw rw rw rw rw rw rw rw rw rw rw bit value sub frame number which is added 1 clock pulse count if bit0=1 32 1 if bit1=1 16, 48 2 if bit2=1 8, 24, 40, 56 4 if bit3=1 4, 12, 20, 28, 36, 44, 52, 60 8 if bit4=1 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 16 if bit5=1 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 32 table 14-1 pwm8l and sub frame matching table main pwm frame ..... 012 616263 sub pwm frame sub pwm frame which is added 1 clock 1 clock width : ps2
HMS81C43XX / gms87c4060 49 november 2001 ver 1.2 figure 14-6 14bit pwm registers 5. pwm output is enabled during en8 bit contains 1. 6. cntb controls pwm counter enable. if cntb=0, counter is enabled. pwm width data register address : 0e8 h reset value : undefined d7 d6 d5 d4 d3 d2 d1 d0 pwm sub-pulse count register pwm8l address : 0e9 h reset value : undefined pwm control register 2 pwmcr2 address : 0eb h reset value : --0- 00-- b pol2 pol1 buzs 14bit pwm polarity 0: positive (pwm from rising edge) 1: negative (pwm from rising edge) pwm8h d5 d4 d3 d2 d1 d0 pwm control register 1 pwmcr1 address : 0ea h reset value : 0000 0000 b en2 en1 en0 en8 cntb en3 en4 en5 14bit counter enable 0: counter run 1: counter stop 14bit pwm enable 0: r51 1: pwm8 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
HMS81C43XX / gms87c4060 50 november 2001 ver 1.2 15. interrupt interval measurement circuit the interrupt interval measurement circuit is shown in fig- ure 15-1 . the interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, edge detec- tor, 8bit counter, measured result storing register, fifo (9bit, 6level) interrupt, control register, etc. the more details about registers are shown figure 15-2 . figure 15-1 block diagram of interrupt interval measurement circuit control the HMS81C43XX/gms87c4060 contains a interrupt in- terval measurement module. 1. select interrupt input pin what you want to measure by set the func1 [00ce h ]. 2. set idcr [00f9 h ] : fifo clear, interrupt mode, inter- rupt edge select, external interrupt select between int3 and int4, sampling clock select. 3. set idcr [00f9 h ] : set idst to start measuring. 4. counter value is stored to idr [00fb h ] when selected edge is detected. after data was written, timer is cleard au- tomatically and it counts continue. 5 . you can select interrupt occuring point by set interrupt mode select bit (ims), every edge what you selected or fifo 4 level is filled. 6. if input signals interval is larger than maximum counter value (0ff h ), counter occurring an interrupt and count again from 00 h . 7. see figure 15-4 fifo operating mechanism. mux idcr [f9 h ] i34h i34l isel idck idst idfs [fa h ] int3 int4 8bit counter fifo (9bit, 6level) intv ims 1 0 dpol foe fful femp fclr mux ps8 ps9 1 0 mux 0 1 edge detector clear idr [fb h ] d7 d6 d5 d4 d3 d2 d1 d0 overflow 8 4 fclr
HMS81C43XX / gms87c4060 51 november 2001 ver 1.2 figure 15-2 int. interval measurement registers figure 15-3 setting for measurement figure 15-4 example for fifo operating mechanism idr address : 00fb h reset value : undefined interrupt interval determination idcr address : 00f9 h reset value : 0000 -000 b counter control 0: stop 1: clear & count sampling clock select 0: ps9 1: ps8 int. occuring time 0: every selected i34h i34l fclr isel idck idst ims see figure 15-3 d7 d6 d5 d4 d3 d2 d1 d0 r24/int3 port function select register 1 func1 address : 00ce h reset value : -000 0000 b 0: r24 1: int3 int4s int3s int2s int1s int0s ec2s ec3s control register external interrupt select 0: int3 1: int4 fifo clear 0: ignored 1: clear and return to 0 edge by i34h/l 1: every fifo 4level is filled is filled interrupt interval determination idfs address : 00fa h reset value : 1--- -001 b fifo empty flag 0: data filled 1: empty fifo full flag 0: not full 1: full dpol foe fful femp fifo status register fifo overrun error flag 0: no error 1: error detected data polarity 0: data is stored every falling edge interrupt interval determination fifo data register 1: data is stored every rising edge r26/int4 0: r26 1: int4 rw rw rw rw rw rw rw r rrr rrr r rrrr wwwwwww item symbol i34h i34l detecting edge frame cycle 10 rising edge 01 falling edge pulse width 1 1 both edge 1 1 both edge interrupt input 1) fifo storing mechanism 2) fifo reading mechanism femp=1, fful=0 femp=0, fful=0 femp=0, fful=0 femp=0, fful=1 femp=0, fful=1 femp=0 femp=0 femp=1 read out read out data in data in data in data in data 6 will be erased. data 1 data 1 data 2 data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 2 data 1 data 2 data 3 data 4 data 5 data 7 foe=1 (over run error)
HMS81C43XX / gms87c4060 52 november 2001 ver 1.2 16. buzzer driver the buzzer driver circuit is shown in figure 16-1 . the buzzer driver circuit consists of the 6bit counter, 6bit comparator, buzzer data register bur(00ee h ). the bur register controls source clock and output frequency. the more details about registers are shown figure 16-2 . figure 16-1 block diagram of buzzer driver circuit control the HMS81C43XX/gms87c4060 contains a buzzer driv- er module. 1. select an input clock among ps4~7 by set the buck1~0 of bur. 2. select output frequency by change the bu5~0. output frequency = 1 / (psx * buy *2) hz. x=4~7, y=5~0 see example table 16-1 and table 16-2. note: do not select 00 h to bu5~0. it means counter stop. 3. set buzs bit for output enable. 4. output waveform is rectagle clock which has 50% duty. 5. you can use this clock for the other purposes. figure 16-2 buzzer driver registers bur [ee h ] bu5 bu4 bu3 bu2 bu1 bu0 6bit counter output generator buzz buck mux ps4 ps6 ps5 ps7 buck -1 -0 00 01 10 11 clear 6bit comparator clear pwmcr2 [eb h ] buzs pol2 pol1 en7 en6 bur write 6 6 buck1 buck0 clock source 0 0 ps4 0 1 ps5 1 0 ps6 1 1 ps7 buzzer data register bur address : 0ee h reset value : ???? ???? b input select clock select pwm control register 2 pwmcr2 address : 0eb h reset value : --0- 00-- b pol2 pol1 buzs r50/buzz select 0: r50 1: buzz output bu5 bu4 bu3 bu2 bu1 bu0 buck buck -1 -0 wwwwwwww rw rw rw
HMS81C43XX / gms87c4060 53 november 2001 ver 1.2 bur5~0 output frequency (khz) dec hex ps4 ps5 ps6 ps7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 250 125 83.333 62.5 50 41.666 35.714 31.25 27.728 25 22.728 20.834 19.23 17.858 16.666 15.626 14.706 13.888 13.158 12.5 11.904 11.364 10.87 10.416 10 9.616 9.26 8.928 8.62 8.334 8.064 7.812 7.576 7.352 7.124 6.944 6.756 6.578 6.41 6.25 6.098 5.952 5.814 5.682 5.556 5.434 5.32 5.208 5.102 5 4.902 4.808 4.716 4.63 4.546 4.464 4.386 4.31 4.238 4.166 4.098 4.032 3.968 125 62.5 42.666 31.25 25 20.888 17.858 15.625 13.888 12.5 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.25 5.952 5.682 5.435 5.208 5 4.808 4.63 4.464 4.31 4.167 4.032 3.906 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.66 2.604 2.551 2.5 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 62.5 31.25 20.833 15.625 12.5 10.461 8.928 7.813 6.944 6.25 5.682 5.209 4.808 4.484 4.166 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.718 2.604 2.5 2.404 2.315 2.232 2.155 2.084 2.016 1.953 1.894 1.838 1.786 1.736 1.689 1.645 1.602 1.563 1.524 1.488 1.453 1.421 1.389 1.359 1.33 1.302 1.276 1.25 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 table 16-1 . example for f ex =8mhz bur5~0 output frequency (khz) dec hex ps4 ps5 ps6 ps7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 375 187.5 125 93.75 75 62.5 53.572 46.875 41.666 37.5 34.09 31.25 28.846 26.786 25 23.436 22.058 20.833 19.736 18.75 17.858 17.045 16.304 15.625 15 14.424 13.888 13.393 12.932 12.5 12.096 11.718 11.364 11.03 10.714 10.416 10.136 9.868 9.616 9.375 9.146 8.929 8.72 8.523 8.334 8.152 7.978 7.813 7.654 7.5 7.352 7.212 7.076 6.944 6.818 6.696 6.578 6.466 6.356 6.25 6.148 6.048 5.952 187.5 93.75 62.5 46.875 37.5 31.25 26.786 23.436 20.833 18.75 17.045 15.625 14.423 13.393 12.5 11.719 11.029 10.417 9.868 9.375 8.929 8.523 8.152 7.813 7.5 7.212 6.944 6.696 6.466 6.25 6.048 5.859 5.682 5.515 5.357 5.208 5.068 4.934 4.808 4.688 4.573 4.464 4.36 4.261 4.167 4.076 3.989 3.906 3.827 3.75 3.676 3.606 3.538 3.472 3.409 3.348 3.289 3.233 3.178 3.125 3.074 3.024 2.976 93.75 46.875 31.35 23.436 18.75 15.625 13.393 11.719 10.417 9.375 8.523 7.813 7.211 6.696 6.25 5.859 5.515 5.208 4.934 4.688 4.464 4.261 4.076 3.906 3.75 3.606 3.472 3.348 3.233 3.125 3.024 2.930 2.841 2.757 2.679 2.604 2.534 2.467 2.404 2.344 2.287 2.232 2.18 2.131 2.083 2.038 1.995 1.953 1.913 1.875 1.838 1.802 1.769 1.736 1.705 1.674 1.645 1.616 1.589 1.563 1.537 1.512 1.488 46.875 23.438 15.625 11.719 9.375 7.813 6.696 5.895 5.208 4.688 4.261 3.906 3.606 3.348 3.125 2.930 2.757 2.604 2.467 2.344 2.232 2.131 2.038 1.953 1.875 1.803 1.736 1.674 1.616 1.563 1.512 1.465 1.420 1.379 1.339 1.302 1.267 1.234 1.202 1.172 1.143 1.116 1.09 1.065 1.042 1.019 0.997 0.977 0.957 0.938 0.919 0.901 0.884 0.868 0.852 0.837 0.822 0.808 0.795 0.781 0.768 0.756 0.744 table 16-2 . example for f ex =12mhz
HMS81C43XX / gms87c4060 54 november 2001 ver 1.2 17. on screen display (osd) the on screen display circuit is shown in figure 17-1 . the HMS81C43XX/gms87c4060 can support 512 osd chacters, but the last 6 characters (number 506 ~ 511, 1fa h ~ 1ff h ) are reserved for ic test and its pattern is fixed by manufacturer. so you can use 506 characters for your own. the osd circuit consists of the position attribute register, line register, full screen screen control register, sprite control register, sprite position reigster, i/o polarity regis- ter, sprite ram, font rom, vram, etc. the more details about registers are shown figure 17-2. figure 17-1 block diagram of on screen display circuit l1attr [af0 h ] osd control circuit osdln [ae5 h ] osdcon1 [ae0 h ] osdcon2 [ae1 h ] spvpos [ae8 h ] osdpol [ae2 h ] line 1,2 attribute, position register line register full screen control sprite position register i/o polarity register sprite control register register l1vpos [af1 h ] l2attr [af3 h ] l2vpos [af4 h ] sphpos [ae9 h ] lhpos [ae6 h ] horizontal position register fdwset [ae3 h ] field detection register edgecol [ae4 h ] edge color register vram font rom sprite control circuit sprite ram osd, sprite generation circuit sprite control circuit output control circuit synchronization circuit hsync vsync osc1 osc2 r g b i ys ym color mode register colmod [0aef h ] mesh control register meshcon [0aeb h ]
HMS81C43XX / gms87c4060 55 november 2001 ver 1.2 figure 17-2 osd character font example character(foreground) background characte(foreground) outline character shadow background shadow - 16 color with half intensity - color selecting: vram n-character bit19~16(see vram) - 16 color with half intensity - color selecting :vram n-character bit23-20(see vram) - controled by lnattr register(see lnattr) - 16 color with half intensity - color selecting : edgecol register(see edgecol) - controlled by vram n-character bit15-12 - controlled by lnattr register(see lnattr) and - color selecting : edgecol register(see edgecol) - 16 color with half intensity vram n-character bit11-10(see vram) - color selecting : edgecol(see edgecol) - 16 color with half intensity (no character outline case)
HMS81C43XX / gms87c4060 56 november 2001 ver 1.2 figure 17-3 osd control registers - 1 osdcon1 bit 0: stock it controls osd lc oscillation. if oscillation is stoped, ics power consumption is decreased. bit 1: ddclk if you set this bit to 1, osd input clock is doubled from lc oscillation. it makes osd horisontal image size as dou- bled. bit 2: dline if you set this bit to 1, osd vertical scan counter input clock is doubled from normal state. it makes osd vertical image size as doubled. bit 7~3: fullm, i, b, g, r it controls back ground color as below. osdcon2 bit 0: osdon it controls osd, sprite, full screen background at once. it does not affect anything to vsync interrupt and osd inter- rupt, etc. bit 1: prosd it controls screen output priority between sprite and osd. if its value is 1, osd hide sprite pattern in overapped area. bit 2: ensp it enables sprite display. bit 3: dusp it doubles sprites horizontal & vertical size during this value is 1. bit 4: onl1 it enables osd line 1 display. if it is enabled, osd inter- rupt is activated. bit 5: onl2 it enables osd line 2 display. if it is enabled, osd inter- rupt is activated. bit 6: obgw it controls characters width. default width is 12dots. if its value is set, 2 dots (background color) are added both left m i b g r color 0 0 0 0 0 transparent (normal tv) 00001 red table 17-1 full screen back ground color selection sprite osd control register osdcon2 address : 0ae1 h reset value : 0000 0000 b full screen control register osdcon1 address : 0ae0 h reset value : 0000 0000 b stop osd clock 0: release 1: stop fulb fulg fulr dline ddclkstock fuli obgw onl2 onl1 dusp ensp pro osd fulm double dot clock mode 0: normal 1: double double scan line mode 0: normal 1: double full screen background fullm fulli fullb fullg fullr : half blank : half intensity : blue : green : red osd, sprite 0: all off 1: all on priority 0: sprite > osd 1: osd > sprite sprite enable 0: disable 1: enable sprite size 0: normal 1: double background width 0: 12dots 1: 14dots osd line 2 0: off 1: on osd line 1 0: off 1: on per 1 character rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw dusp cl rw sd on double sprite dot clock (sprite size) 0: x1, x2 1: x2, x4 00010 green 0 0 0 1 1 red+green 0 0 1 0 0 blue 0 0 1 0 1 blue+red 0 0 1 1 0 blue+green 0 0 1 1 1 red+green+blue (white) 0 1 0 0 0 black 0 1 0 0 1 half intensity red 0 1 0 1 0 half intensity green 0 1 0 1 1 half intencity red+green 0 1 1 0 0 half intensity blue 0 1 1 0 1 half intensity green+blue 0 1 1 1 1 half intensity white 1 0 0 0 0 half blank m i b g r color table 17-1 full screen back ground color selection
HMS81C43XX / gms87c4060 57 november 2001 ver 1.2 and right side of character. bit 7: duspcl it controls sprites dot clock and scan line speed. it does not affect to osd. sprite size is controlled as below. figure 17-4 osd registers - 2 osdpol bit7~0 : pol hs, vs, i, ym, ys, b, g, r it controls hs, vs, i, ym, ys, b, g, r ports polarity. if its value is 1, polarity is active high. fdwset fdwset (field detection window seting) register de- tects the begin of vsync(vertical sync.) signal and distin- guishs its current field is even field or odd field. figure 17-5 fdwset detection region the region of fmin[2:0] ~ fmax[3:0] is field detection window. fmax[3:0] can divide the region between hsync(hori- zontal sync.) by 16. you can assume there is 4 bit horizon- tal counter, for example hcount[3:0] which count 0~15. if the start of vsync is detected at the window, next field is even. else if vsync is detected another region of the window, next field is odd. it means start of vsync is detected during fmin[2:0] < hcount[3:0] < fmax[3:0] and fpol value is 0, it dis- tinguish odd field. and, start of vsync is detected during fmin[2:0] < hcount[3:0] < fmax[3:0] and fpol value is 1, it dis- tinguish even field. fmin[2:0], fmax[3:0] are compared with the horizontal counter in osd block. duspcl dusp size 0 0 normal 12x16 0 1 x 2 24x32 1 0 not used - 1 1 x 4 48x64 table 17-2 sprite pattern size i/o polarity ( initial ) register osdpol address : 0ae2 h reset value : undefined pol poli pol pol polb polg polr pol ys ym vs hs 0: active low 1: active high osd display enable, polhs polvs poli polym polb polg polr : hsync. input : vsync. input : half intensity output : half blank output : blue output : green output : red output include the edge color. 0: off 1: on field detection register fdwset address : 0ae3 h reset value : 0111 1010 b fpol fmin2 ~ 0 fmax3 ~ 0 field detection polarity 0: detect odd field field detection maximum pointer field detection minimum pointer masking range : min.~max. 1: detect even field detecting range : min.~max. wwwwwwww wwwwwwww hsync ex1: vsync(odd) ex2: vsync(even) fmin fmax
HMS81C43XX / gms87c4060 58 november 2001 ver 1.2 figure 17-6 osd registers - 3 figure 17-7 osd registers - 4 l1attr bit 0 : liv8 it is equivalent with l1vposs bit 8. see more details in l1vpos. bit 1: fsc1 it selects character outline and shadow color. if it is 1, it se- lect edge2 color in edgecol register. or not, it select edge1 color. according to edgecol register and this bit character and shadow colors are selected simulteneous- ly bit 3~2: csz11~csz10 it controls osd characters size ( x1, x2, x3). you can use this register and ddclk, dline bit, horizontal / vertical size can be controlled (x2, x4, x6). bit 4: ensh1 it enables line 1s character(foreground) shadow. bit 5: enol1 it enables line 1s character(foreground) outline. bit 6: wdsl1 it shows thickness of line 1s shadow and outline. bit 7: obgh1 it controls characters height. default height is 16dots. if its value is set, 2 dots (background color) are added both top and bottom side of character. osd line register osdln address : 0ae5 h reset value : ---0 0000 b background shadow / edge edgecol address : 0ae4 h reset value : undefined edgni edg edge 2 color vlr4 ~ 0 color register 2i edg 2b edg 2g edg 2r edg 1i edg 1g edg 1r edg 1b edge 1 color edgnb edgng edgnr : half intensity : blue : green : red n : 1 ~ 2 current displayed osd line number ( 00000 ~ 11111 b : 0 ~ 63 ) osd line horizontal lhpos address : 0ae6 h reset value : undefined osd lines horizontal position (00 ~ ff h ) sprite vertical spvpos address : 0ae8 h reset value : undefiend sprite horisontal sphpos address : 0ae9 h reset value : undefined position register position register position register d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sprites vertical position (00 ~ ff h ) sprites horisontal position (00 ~ ff h ) wwwwwwww rrrrr wwwwwwww wwwwwwww wwwwwwww osd line 1s l1vpos address : 0af1 h reset value : undefined osd line 1s l1attr address : 0af0 h reset value : undefined vertical position foreground shadow enol ensh csz csz fsc1 l1v8 wdsl character size l1v7 l1v6 l1v5 l1v4 l1v3 l1v2 l1v1 l1v0 attribute register vertical position register osd line 1s vertical position (include l1v8 : 000 ~ 1ff h ) obgh 111111 10 l1vposs bit8 out line color 0: edge 1s color 1: edge 2s color 00: normal 01: 2 times 10: 3 times 11: reserved character shodow 0: disable 1: enable charcater outline 0: disable 1: enable shadow / outline 0: 1dot 1: propotional character 0: 16dots 1: 18dots background height width to character size wwwwwwww www w wwww control control wdsl enol ensh outline, shadow 0 0 0 no outline, no shadow 0 0 1 thin shadow 0 1 0 thin outline 01 1 thin outline thick shadow 1 0 0 no outline, no shadow 1 0 1 thick shadow 1 1 0 thick outline 11 1 thick outline thick shadow table 17-3 character outline, shadow table
HMS81C43XX / gms87c4060 59 november 2001 ver 1.2 l1vpos it shows osd line 1s vertical position in 9bit format (liv8 + l1vpos, 000 ~ 1ff h ). figure 17-8 osd registers - 5 figure 17-9 osd register - 6 l2attr it controls osd line 2s attributes. its function is the same as l1attr. l2vpos it shows osd line 2s vertical position. its function is the same as l1vpos. colmod it controls osd output mode-rgb direct half intencity. figure 17-10 osd register - 7 bit 0: c16en it enables rgb port half intencity output. when this bit is set, rgb port generates half intencity output. half intenci- ty output is 3.5v voltage level output of rgb port. when you use this bit, you must fill all the other bit with 0. note: when you do not use rgb direct half intncsity out- put , please initialize this register as 00h. meshcon it controls osd mesh mode color. figure 17-11 osd register - 8 note: please initialize this register as 00h. though this register is for mesh mode color, it is not used currently. vram vram contains 1 osd line, 24 characters attributes. each characters attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, char- acter and character number ( 000 h ~ 1ff h , 512 characters osd line 2s l2vpos address : 0af4 h reset value : undefined osd line 2s l2attr address : 0af3 h reset value : undefined vertical position foreground shadow enol ensh csz csz fsc2 l2v8 wdsl character size l2v7l2v6l2v5l2v4l2v3l2v2l2v1l2v0 attribute register vertical position register osd line 2s vertical position (include l2v8 : 000 ~ 1ff h ) obgh 22222120 l2vposs bit8 out line color 0: edge 1s color 1: edge 2s color 00: normal 01: 2 times 10: 3 times 11: reserved shodow control 0: disable 1: enable out line control 0: disable 1: enable shadow / outline 0: 1dot 1: propotional character 0: 16dots 1: 18dots background height width to character size www w wwww wwwwwwww osd line 2s l2vpos address : 0af4 h reset value : undefined osd line 2s l2attr address : 0af3 h reset value : undefined vertical position foreground shadow enol ensh csz csz fsc2 l2v8 wdsl character size l2v7l2v6l2v5l2v4l2v3l2v2l2v1l2v0 attribute register vertical position register osd line 2s vertical position (include l2v8 : 000 ~ 1ff h ) obgh 22222120 l2vposs bit8 out line color 0: edge 1s color 1: edge 2s color 00: normal 01: 2 times 10: 3 times 11: reserved shodow control 0: disable 1: enable out line control 0: disable 1: enable shadow / outline 0: 1dot 1: propotional character 0: 16dots 1: 18dots background height width to character size wwwwwwww w wwww www color output mode colmod address : 0aef h reset value : undifined rgb half intensity enable c16en register w 1: enable 0: enable (see note) fill with 0 mesh mode color meshcon address : 0aeb h reset value : see note register
HMS81C43XX / gms87c4060 60 november 2001 ver 1.2 ), etc. note: if (bsl = 1) & (bscul = 0) & (lnattr,enshn = 1), then the right bottom shadow of font character is shifted to 1 dot right side. this shadow effect will continue until that (bsr) of adjacent character attribution become (bsr = 1). line no. character no. address (bit 23~0) hexa decimal 1 1 a40 a20 a00 2 a41 a21 a01 3 a42 a22 a02 :::: 22 a55 a35 a15 23 a56 a36 a16 24 a57 a37 a17 2 1 ac0 aa0 a80 2 ac1 aa1 a81 3 ac2 aa2 a82 :::: 22 ad5 ab5 a95 23 ad6 ab6 a96 24 ad7 ab7 a97 table 17-4 vram memory map bit no. name function 15 bsr enable right side background shadow. cf . if bsl=1 and bscul=1 and lnattr.enshn=1, characters right bottom shadow is shifted to right side by 1dot unit. it acts continued until current characters right side chacters bsr is set to 1. 14 bsl enable left side background shadow. 13 bsd enable bottom side background shadow. 12 bsu enable top side background shadow. 11 bscdr select color of right and bottom side shadow of the background 0: edge1, 1: edge2 color table 17-5 vram (bit15~0) function 10 bscul select color of left and top side shadow of the background 0: edge1, 1: edge2 color 9 enrnd enable characters rounding 8~0 cg8~0 character font number ( among 000 ~ 1ff h ) bit no. & name output ( polarity : through) character color 19 18 17 16 ibgr y m y s ibgr 0000000000 clear 0001010001 red 0010010010 green 0011010011 yellow 0100010100 blue 0101010101 m agenta 0110010110 cyan 0111010111 white 1000010000 black 1001010001 half-i,red 1010010010half-i,green 1011010011 half-i, yellow 1100010100 half-i,blue 1101010101 half-i, magenta 1110010110half-i,cyan 1111010111half-i,white table 17-6 vram (bit19~16) function bit no. name function table 17-5 vram (bit15~0) function
HMS81C43XX / gms87c4060 61 november 2001 ver 1.2 font rom the HMS81C43XX/gms87c4060 osd character size is fixed as 12dots (horisontal) * 16dots (vertical). 1. each horisontal data (12dots) needs 2byte rom. 2. one character is constructed with 16 horisontal data to vertically. as a result, one character needs 32bytes (2 * 16 bytes). 3. hms81c4332/gms87c4060 contains 256/512 charac- ters. total font rom memory size is calulated as 16,384bytes ( 32bytes / character * 512 character ) 4. font rom memory is located from 10000 h ~ 13fff h , this memory can not be accessed by user program. 5. a characters address and dot position in font rom is described in figure 17-12 . figure 17-12 example for a character (53 h ) sprite ram the HMS81C43XX/gms87c4060 contains a 32bytes (12dot * 16dot) sprite ram. 1. in view point, sprite is similar to character font but it is not using font rom. 2. you can selct color by dot unit. 3. using above 1 and 2, you can make any of patterns what you want by software. for example, arrow cursor or some- bit no. & name output ( polarity : through) back ground color 23 22 21 20 ibgr y m y s ibgr 0000000000 clear 0001010001 red 0010010010 green 0011010011 yellow 0100010100 blue 0101010101 m agenta 0110010110 cyan 0111010111 white 1000100000 half blanking 1001011001half-i,green 1010011010 half-i, yellow 1011011011 half-i,blue 1100011100 half-i, magenta 1101011101half-i,cyan 1110011110half-i,white 1111010111 black table 17-7 vram (bit 23 ~ 20) function charact er code address range upper 4bit lower 8bit 000 h 12000 h ~ 1200f h 10000 h ~ 1000f h 001 h 12010 h ~ 1201f h 10010 h ~ 1001f h 002 h 12020 h ~ 1202f h 10020 h ~ 1002f h :: : xyz h (12000h + xyz0h) ~ (12000h + xyzfh) (10000h + xyz0h) ~ (10000h + xyzfh) :: : 1fd h 13fd0 h ~ 13fdf h 11fd0 h ~ 11fdf h 1fe h 13fe0 h ~ 13fef h 11fe0 h ~ 11fef h 1ff h 13ff0 h ~ 13fff h 11ff0 h ~ 11fff h table 17-8 font rom memory map msb lsb address 12530 h 12531 h 12532 h 12533 h 12534 h 12535 h 12536 h 12537 h 12538 h 12539 h 1253a h 1253b h 1253c h 1253d h 1253e h 1253f h 00 h 07 h 08 h 08 h 08 h 09 h 0b h 08 h 08 h 08 h 08 h 08 h 08 h 08 h 07 h 00 h data address 10530 h 10531 h 10532 h 10533 h 10534 h 10535 h 10536 h 10537 h 10538 h 10539 h 1053a h 1053b h 1053c h 1053d h 1053e h 1053f h 00 h fe h 01 h 61 h f1 h f9 h fd h 61 h 61 h 61 h 61 h 61 h 61 h 01 h fe h 00 h data
HMS81C43XX / gms87c4060 62 november 2001 ver 1.2 thing. 4. sprite position is controlled by sprite position register spvpos[0ae8 h ] and sphpos[0ae9 h ]. 5. sprite ram is located 0c00~0cf5 h . one sprite ram byte contains 2 dots color data. see more details in table 17-9 ~ table 17-11. test font HMS81C43XX use first osd font as test purpose(see fig17-13). when you design osd characte font, you incert following font to font rom 00h. if you like to use this font originally, please contact us figure 17-13 test font pattern column number row number msb ~ lsb 00 h 0c05 h ~ 0c00 h 01 h 0c15 h ~ 0c10 h 02 h 0c25 h ~ 0c20 h :: ~ : 0n h (n=0~f) 0cn5 h ~ 0cn0 h :: ~ : 0e h 0c05 h ~ 0c00 h 0f h 0c05 h ~ 0c00 h table 17-9 sprite ram address map odd dot color even dot color bit no. 76543210 function -bgr-bgr table 17-10 a sprite rams contents b g r color 000 clear 001 red 010 green 011 yellow 100 blue 101 black 110 cyan 111 white table 17-11 sprite ram color table 1000h 00h 1001h 00h 1002h 00h 1003h f8h 1004h fch 1005h 0eh 1006h 06h 1007h 06h 1008h 06h 1009h 06h 100ah 06h 100bh 06h 100ch 0eh 100dh fch 100eh f8h 100fh 00h 1200h 00h 1201h 00h 1202h 00h 1203h 01h 1204h 03h 1205h 07h 1206h 06h 1207h 06h 1208h 06h 1209h 06h 120ah 06h 120bh 06h 120ch 07h 120dh 03h 120eh 01h 120fh 00h msb lsb address data address data
HMS81C43XX / gms87c4060 63 november 2001 ver 1.2 18. i 2 c bus interface the i 2 c bus interface circuit is shown in figure 18-1 . the multi-master i 2 c bus interface is a serial communica- tions circuit, conforming to the phlips i 2 c bus data trans- fer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. this multi-master i 2 c bus interface circuit consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c sta- tus register and other control circuits. the more details about registers are shown figure 18-2 ~ figure 18-6 . figure 18-1 block diagram of multi-master i 2 c circuit control the HMS81C43XX/gms87c4060 contains two i 2 c bus interface modules. it supports multi-master function, so it contains arbitration lost detection, synchronization func- tion,etc. i 2 c address register it contains slave address (7bit) which is used during slave mode and read/write bit. bit 7 ~ 0 : slave address 6~0 note: bit 7~0 (sad6~0) store slave address. the address data transmitted from the master is compared with the con- tents of these bits. icar [d8 h ] ifi2cr bit counter scl address comparator icdr [d9 h ] d7 d6 d5 d4 d3 d2 d1 d0 interrupt generation circuit data control circuit icsr [00da h ] mst trx bb pin al aas ad0 lrb noise elimination circuit al circuit bb circuit clock control circuit noise elimination circuit iccr1 [00db h ] bsel1~0 als eso bc2~0 iccr2 [dc h ] aclk ack 1 ccr3~0 clock division external clock sda sad6 sda5 sda4 sda3 sda2 sda1 sda0 r/w item function format philips i 2 c standard 7bit addressing format communication mode master transmitter master receiver slave transmitter slave receiver scl clock frequency 66.6khz ~ 500khz (f ex =12mhz) 44.4khz ~ 333.3khz (f ex =8mhz) item function
HMS81C43XX / gms87c4060 64 november 2001 ver 1.2 figure 18-2 i 2 c address register i 2 c data shift register [icdr] the i 2 c data shift register is an 8bit shift register to store received data and write transmit data. when transmit data is written into this register, it is trans- fered to the outside from bit7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is re- ceived, it is input to this register from bit0 in synchroniza- tion with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00dc h ) is 1. the bit counter is reset by a write instruc- tion to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled regardless of the eso bit value. figure 18-3 data shift register i 2 c status register the i 2 c status register controls the i 2 c bus interface sta- tus. the low-order 4bits are read only bits and the high-or- der 4bits can be read out and written to. the more details about its bits are shown table 18-1. icar address : 00d8 h reset value : 0000 0000 b sad6 sda5 sda4 sda3 sda2 sda1 sda0 r/w slave address rw rw rw rw rw rw rw r icdr address : 00d9 h reset value : 0000 0000 b rw rw rw rw rw rw rw rw d7 d6 d5 d4 d3 d2 d1 d0 shift left 1-bit each s cl bit no. name function 7 6 mst trx 00: slave / receiver mode 01: slave / transmitter mode 10: master / receiver mode 11: master / transmitter mode mst is cleared when - after reset. - after the arbitration lost is occured and 1 byte data transmission is finished. - after stop condition is detected. - when start condition is disabled by start condition duplication preventation function. trx is cleared when - after reset. - when arbitration lost or stop condition is occured . - when mst is 0, and start condition or ack non-return mode is detected. 5bb bb(bus busy)bit is 1 during bus is busy. this bit can be written by s/w. its value is 1 by start condition, and cleared by stop condition. 4pin pin(pending interrupt not)bit is inter- rupt request bit. if i 2 c interrupt request is issued, its value is 0. pin is cleared when - after 1 byte trasmission / receive is fin- ished. pin is set when - after reset. - after write instruction is excuted into i 2 c data shift register icdr. - when pin bit low, the output of scl is pulled down, so if you want to release scl, you must perform write instruction cdr. 3al arbitration lost detection flag. if arbitration lost is detected, al=1, or 0. 2 aas slave address comparison flag. it shows compared result with received address data and i 2 c address register (icar). it is 1, when two of data is same. table 18-1 bit function
HMS81C43XX / gms87c4060 65 november 2001 ver 1.2 figure 18-4 i 2 c status register i 2 c control register 1 it controls communication data format. figure 18-5 i 2 c control register 1 i 2 c control register 2 it controls scl mode, scl frequency, etc. it contains 8bit data to transmit to external device when tr- asmitter mode, or received 8bit data from external device when receive mode. 1ad0 general call detection flag. if general call is detected, ad0=1, or not 0. * general call : if received address is all 0 . it is called general call. 0lrb last received bit. it is used for receive confirmation. if ack is returned, lrb=0, or not 1. bit no. name function 7 6 bsel1 bsel0 i 2 c connection control. 00: no connection 01: scl1, sda1 10: scl2, sda2 11: scl1, sda1, scl2, sda2 4als data format selection. 0: addressing format 1: free data format 3 eso i 2 c bus interface use enable flag 0: disabled 1: enabled 2bc2 bit counter. 000 b : 8bit 001 b ~111 b : 1~7bit 1bc1 0bc0 table 18-2 bit function bit no. name function table 18-1 bit function icsr address : 00da h reset value : 0001 0000 b rw rw rw rw r rrr mst trx bb pin al aas ad0 lrb bit no. name function 7aclk select acknowledge clock (ack) mode. 0: no acknowledge clock mode. acknowledge clock is not generated after data was transmismitted. 1: acknowledge clock mode. acknowledge clock is generated after data was transmismitted. 6ack if acknowledge clock is returned, this bit is 0. or not 1. 5 1 (fixed) not used. table 18-3 bit function iccr1 address : 00db h reset value : 00-0 0000 b als eso bc2 bc1 bc0 bsel bsel 10 rw rw rw rw rw rw rw
HMS81C43XX / gms87c4060 66 november 2001 ver 1.2 figure 18-6 i 2 c control register 2 figure 18-7 interrupt request signal generation timing start condition generation when the eso bit of the i 2 c control register (00db h ) is 1, writing to the i 2 c status register will generate start condition. refer to figure 18-8 for the start condition generation timing diagram. figure 18-8 start condition generation timing restart condition generation restart conditions setting sequence is as followings. 1. write 020 h to i 2 c status register (icsr, 00da h ) 2. write slave address to i 2 c data shift register (icdr, 00d9 h ) 3. write 0f0 h to i 2 c status register (icsr, 00da h ) stop condition generation writing c0h to icsr will generate a stop condition, 3 2 1 0 ccr3 ccr2 ccr1 ccr0 scl frequency selection scl frequency = f ex / (12 * ccr) value f ex = 12mhz f ex = 8mhz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not allowed not allowed 500.0khz 333.3khz 250.0khz 200.0khz 166.6khz 142.9khz 125.0khz 111.1khz 100.0khz 90.0khz 83.3khz 76.4khz 71.4khz 66.6khz not allowed not allowed 333.3khz 222.2khz 166.6khz 133.3khz 111.1khz 95.2khz 83.3khz 74.1khz 66.6khz 60.6khz 55.5khz 51.3khz 47.6khz 44.4khz bit no. name function table 18-3 bit function iccr2 address : 00dc h reset value : 000- 0000 b rw rw rw rw rw rw aclk ack 1 ccr3 ccr2 ccr1 ccr0 scl pin i 2 c request icsr write signal scl sda bb (bus busy) flag t setup t hold t bb : setup time : hold time : set time for bb t setup t hold t bb (i 2 c status reg.)
HMS81C43XX / gms87c4060 67 november 2001 ver 1.2 w h e n e s o ( i c c r b i t 3 ) i s 1 figure 18-9 stop condition generating timing diagram start / stop condition generation time is shown table 18-4. start / stop condition detect start / stop condition is detected when table 18-4 is satisfied. figure 18-10 start / stop condition detection timing start / stop detection time is showed table 18-5. item timing spec. setup time ( t setup ) 3.3us (n=20cycles) hold time ( t hold ) 3.3us (n=20cycles) set/reset time for bb flag ( t bb ) 3.0us (n=18cycles) table 18-4 example time ( f ex =12mhz ) icsr write signal scl sda bb (bus busy) flag t setup t hold t bb : setup time : hold time : set time for bb t setup t hold t bb (i 2 c status reg.) item timing spec. scl release time > 2.0us (n=12cycles) setup time > 1.0us (n=6cycles) hold time > 1.0us (n=6cycles) table 18-5 example time ( f ex =12mhz ) scl sda (start) sda (stop) t setup t hold : setup time : hold time t setup t hold scl release time
HMS81C43XX / gms87c4060 68 november 2001 ver 1.2 address data communication the first transmitted data from master is compared with i 2 c address register (icar, 00d8 h ). at this time r/w is not compared but it determines next data operation. i.e, transmitting or receiving data figure 18-11 address data communication format master -> slave (with 7bit address) start r/w ack ack ack /ack data stop slave addr. slave -> master (with 7bit address) data block from master to slave data block from slave to master 7bit data start r/w ack ack ack data stop slave addr. 7bit data (1) (0)
HMS81C43XX / gms87c4060 69 november 2001 ver 1.2 19. interrupts the HMS81C43XX/gms87c4060 interrupt circuits con- sist of interrupt enable register (ienh, ienl), interrupt re- quest flags of irqh, irql, priority circuit and master enable flag ("i" flag of psw). 16 interrupt sources are pro- vided. the configuration of interrupt circuit is shown in figure 19-2 . below table shows the interrupt priority the external interrupts can each be transition-activated (1- to-0 or 0-to-1 transition). when an external interrupt is generated, the flag that gen- erated it is cleared by the hardware when the service rou- tine is vectored to only if the interrupt was transition- activated. the timer/counter interrupts are generated by tnif(n=0~3), which is set by a match in their respective timer/counter register. the basic interval timer interrupt is generated by bitif which are set by a overflow in the timer register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flags (in irqh,irql) except power-on reset and software brk in- terrupt. interrupt mode register it controls interrupt priority. it takes only one specified in- terrupt. of course, interrupts priority is fixed by h/w, but some- times user want to get specified interrupt even if higher priority interrupt was occured. higher priority interrupt is processed the next time. it contains 2bit data to enable priority selection and 4bit data to select specified interrupt. figure 19-1 interrupt mode register reset/interrupt symbol priority hardware reset external interrupt 0 osd interrupt external interrupt 1 external interrupt 2 timer/counter 0 timer/counter 2 1 frame interrupt vsync interrupt timer/counter 1 timer/counter 3 interrupt interval measure watchdog timer basic interval timer serial i/o interrupt i 2 c interrupt reset int0 osd int1 int2 timer 0 timer 2 1frame vsync timer 1 timer 3 intv(int3/4) wdt bit sio i2c - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bit no. name value function 5,4 im1~0 00 01 1x mode 0: h/w priority mode 1: s/w priority interrupt is disabled, even if ie is set. 3~0 ip3~0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 int0 osd int1 int2 timer 0 timer 2 1frame vsync timer 1 timer 3 intv(int3/4) wdt bit sio i2c not used table 19-1 bit function imod address : 00f3 h reset value : undefined im0 ip3 ip2 ip1 ip0 rw rw rw rw rw rw im1
HMS81C43XX / gms87c4060 70 november 2001 ver 1.2 figure 19-2 block diagram of interrupt t0 timer 0 int2 int1 int2 int1 ifosd osd int0 int0 ienh [00f6 h ] interrupt enable irqh interrupt vector address generator internal bus line register (higher byte) to cpu interrupt master enable flag i flag priority control i-flag is in psw , it is cleared by "d i", set by "ei" instruction. w hen it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "r eti" instruction, i-flag is set to "1" by hardware. t2 timer 2 1frame 1 frame vsync ifvsync wdt ifwdt ifbit ifs bit sr ifi2c i2c ienl [00f4 h ] irql intv intr. interval t3 timer 3 t1 timer 1 [00f5 h ] internal bus line imod [00f3 h ] bit5 interrupt enable register (lower byte) reset brk [0f7 h ]
HMS81C43XX / gms87c4060 71 november 2001 ver 1.2 interrupt enable registers are shown in figure 19-4 . these registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. when enable flag is "0", a corre- sponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which disables all interrupts at once. figure 19-3 interrupt request flags int2 r/w int0 vsync interrupt request flag initial value: 0000 0000 b address: 00f7 h irqh osd msb lsb 1frame vsync t0 t2 int1 r/w r/w wdt r/w t1 initial value: 0000 000- b address: 00f5 h irql t3 msb i2c bit intv r/w r/w r/w sr r/w r/w r/w r/w r/w r/w r/w r/w 1 frame interrupt request flag timer / counter 2 interrupt request flag timer / counter 0 interrupt request flag external interrupt 2 interrupt request flag external interrupt 1 interrupt request flag on screen display interrupt request flag external interrupt 0 interrupt request flag i 2 c interrupt request flag lsb serial i/o interrupt request flag basic interval timer interrupt request flag watch-dog timer interrupt request flag interrupt interval measurement interrupt request flag (int3/4) timer / counter 3 interrupt request flag timer / counter 1 interrupt request flag
HMS81C43XX / gms87c4060 72 november 2001 ver 1.2 figure 19-4 interrupt enable flags int2 r/w int0 vsync interrupt enable flag initial value: 0000 0000 b address: 00f6 h ienh osd msb lsb 1frame vsync t0 t2 int1 r/w r/w wdt r/w t1 initial value: 0000 000- b address: 00f4 h ienl t3 msb i2c bit intv r/w r/w r/w sr r/w r/w r/w r/w r/w r/w r/w r/w 1frame interrupt enable flag timer / counter 2 interrupt enable flag timer / counter 0 interrupt enable flag external interrupt 2 interrupt enable flag external interrupt 1 interrupt enable flag on screen display interrupt enable flag external interrupt 0 interrupt enable flag i 2 c interrupt enable flag lsb serial i/o interrupt enable flag basic interval timer interrupt enable flag watch-dog timer interrupt enable flag interrupt interval measurement interrupt enable flag (int3/4) timer / counter 3 interrupt enable flag timer / counter 1 interrupt enable flag
HMS81C43XX / gms87c4060 73 november 2001 ver 1.2 19.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an in- struction. interrupt acceptance sequence requires 8 f ex (2 m s at f main =4mhz) after the completion of the current in- struction execution. the interrupt service task terminates upon execution of an interrupt return instruction [reti]. interrupt acceptance figure 19-5 interrupt service routine entering timing 1. the interrupt master enable flag (i-flag) is cleared to "0" to temporarily disable the acceptance of any fol- lowing maskable interrupts. when a non-maskable in- terrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to "0". 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decrements 3 times. 4. the entry address of the interrupt service program is read from the vector table address, and the entry ad- dress is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents.
HMS81C43XX / gms87c4060 74 november 2001 ver 1.2 a maskable interrupt is not accepted until the i-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. when nested interrupt service is necessary, the i-flag is set to "1" in the interrupt service program. in this case, accept- able interrupt sources are selectively enabled by the indi- vidual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other reg- isters. these registers are saved by the program if neces- sary. also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; 19.2 brk interrupt software interrupt can be invoked by brk instruction, which is the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 19-6 . figure 19-6 execution of brk/tcall0 intxx: push a push x lda dpgr push a ;save acc. ;save x reg. ;save dpgr ; direct page ; accessable reg. ; : interrupt processing : pop a sta dpgr pop x pop a reti ;restore dpgr ;restore x reg. ;restore acc. ;return basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
HMS81C43XX / gms87c4060 75 november 2001 ver 1.2 19.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. figure 19-7 execution of multi interrupt however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user set i-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#ffh ; enable all interrupts ldm ienl,#feh pop y pop x pop a reti enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
HMS81C43XX / gms87c4060 76 november 2001 ver 1.2 19.4 external interrupt the external interrupt on int0, int1... pins are edge trig- gered depending the edge selection register. refer to 6. port structures on page 10. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. figure 19-8 external interrupt block diagram int0, int1 and int2 are multiplexed with general i/o ports. to use external interrupt pin, the bit of port function register func1 should be set to "1" correspondingly. response time the int0, int1 and int2 edge are latched into int0if, int1if and int2if at every machine cycle. the values are not actually polled by the circuitry until the next ma- chine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. for example, the div instruction takes twelve machine cycles. thus, a minimum of twelve complete ma- chine cycles elapse between activation of an external inter- rupt request and the beginning of execution of the first instruction of the service routine figure 19-9 interrupt response timing diagram ( interrupt overhead ) int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt ieds [00f2 h ] edge selection system clock instruction fetch last instruction execution (0~12cycle) enter interrupt service routine (8cycle) interrupt request sampling 1cycle interrupt overhaed (9~21cycle)
HMS81C43XX / gms87c4060 77 november 2001 ver 1.2 20. watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and re- sumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. figure 20-1 block diagram of watchdog timer watchdog timer control figure 20-2 shows the watchdog timer control register. the watchdog timer is automatically disabled after reset. the cpu malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. re- peatedly clearing the binary counter within the setting de- tection time. if the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter are cleared. at this time, when wdton=1 a reset is generated, which drives the reset pin low to reset the internal hardware. when wdton=0, a watchdog timer interrupt (ifwdt) is generated. figure 20-2 watchdog timer register to reset cpu wdtr watchdog timer register (bit overflow : ifbit) clock source 6-bit up-counter enable wdt 6-bit compare data comparator 6 wdtr[bit5~0] watchdog timer interrupt wdtcl[bit6] clear [00d7 h ] ifwdt ckctlr clock control register [00d6 h ] wdton[bit5] cktclr address : 00d6 h reset value : 0000 0000 b wdt enp btcl bts2 bts1 bts0 watchdog timer on/off control wwwwwr wdtr address : 00d7 h reset value : -011 1111 b wdt wdtr5 ~ 0 slave address wwwwwww on ck 0: normal 6bit timer, watchdog off 1: watchdog timer cl watchdog timer clear 0: watchdog timer free run 1: watchdog timer clear and free run automatically cleared this bit after 1cycle
HMS81C43XX / gms87c4060 78 november 2001 ver 1.2 example: sets the watchdog timer detection time enable and disable watchdog watchdog timer is enabled by setting wdton (bit 5 in cktclr) to "1". wdton is initialized to "0" during re- set, wdton should be set to "1" to operate after reset is released. example: enables watchdog timer reset : ldm cktclr,#001?????b ;wdton ? 1 : : the watchdog timer is disabled by clearing bit 5 (wd- ton) of cktclr. watchdog timer interrupt the watchdog timer can also be used as a simple 6-bit tim- er by clearing bit 5 (wdton) of cktclr. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 6-bit timer interrupt setting up. ldx #03fh txsp ;sp ? 3f ldm cktclr,#000?????b ;wdton ? 0 ldm wdtr,#01??????b ;wdtcl ? 0 : : refer table and see bit timer (). ldm wdtr,#01??????b ; clear counter and set value(??????b) ; you have to set wdtr first, for prevent unpredictable interrupt ; when you set wdton bit. ldm ckctlr,#00111???b ; select clock source(???b) and wdton=1 ldm wdtr,#01??????b ; clear counter : : : : ldm wdtr,#01??????b ; clear counter : : : : ldm wdtr,#01??????b ; clear counter within wdt detection time within wdt detection time
= ckctlr bts2~0 bit input clock watchdog timer input clock ifwdt cycle 000 b ps4 (2us) 512us 32,256us 001 b ps5 (4us) 1,024us 64,512us 010 b ps6 (8us) 2,048us 129,024us 011 b ps7 (16us) 4,096us 258,048us 100 b ps8 (32us) 8,192us 516,096us 101 b ps9 (64us) 16,384us 1,032,192us 110 b ps10 (128us) 32,768us 2,064,384us 111 b ps11 (256us) 65,536us 4,128,768us table 20-1 watchdog timer max. cycle (ex:f ex =8mhz)
HMS81C43XX / gms87c4060 79 november 2001 ver 1.2 figure 20-3 watchdog timer timing minimizing current consumption it should be set properly that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. see figure 20-4 . 2 3 n source clock binary-counter wdtr ifwdt interrupt wdtr ? "0100_0011b" 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
HMS81C43XX / gms87c4060 80 november 2001 ver 1.2 figure 20-4 application example of port under power consumption input pin v dd gnd i v dd output pin gnd i x weak pull-up current flows in the left case, much current flows from port to gnd. x on off v dd internal pull-up output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, low output to the port . input pin i v dd x very weak current flows v dd o o open on off open i=0 o o v dd o i=0 o gnd o when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption.
HMS81C43XX / gms87c4060 81 november 2001 ver 1.2 21. oscillator circuit the HMS81C43XX/gms87c4060 has two oscillation cir- cuits internally. x in and x out are input and output for main frequency and osc1 and osc2 are input and output for osd(on screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 21-1 . figure 21-1 oscillation circuit oscillation components have their own characteristics, so user should consult the component manufacturers for ap- propriate values of external components. in addition, see figure 21-2 for the layout of the crystal. note: minimize the wiring length. do not allow wiring to in- tersect with other signal conductors. do not allow wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. figure 21-2 layout example of oscillator pcb circuit x out x in v ss recommend c1 c2 x out x in external clock open external oscillator lc oscillator crystal oscillator fc (mhz) you have to tune the for selection l,c value, osc2 osc1 v ss frequency to appropriate range which is dependent to your target set. c1 c2 l1 fc (mhz) 4 6 8 c1 & c2 (pf) 30 5 recommend fc (mhz) 8 12 16 c1 & c2 (pf) l (uh) 20 5 20 10 5 100 15 15 15 x out x in
HMS81C43XX / gms87c4060 82 november 2001 ver 1.2 22. reset the HMS81C43XX/gms87c4060 have two types of reset generation procedures; one is an external reset input, other is a watch-dog timer reset. table 22-1 shows on-chip hard- ware initialization by reset action. table 22-1 initializing internal status by reset action 22.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is ap- plied and the internal state is initialized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 22-2 . internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before reading or testing it. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffe h - ffff h . a connecting for simple power-on-reset is shown in figure 22-1 . figure 22-1 simple power-on-reset circuit figure 22-2 timing diagram after reset on-chip hardware initial value on-chip hardware initial value program counter pc (ffff h ) - (fffe h ) peripheral clock off ram page register dpgr 00 h watchdog timer disable g-flag of psw g 0 control registers refer to table 8-1 on page 22 reset + - v dd gnd mcu main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1 fetch ~ ~
HMS81C43XX / gms87c4060 83 november 2001 ver 1.2 22.2 watchdog timer reset refer to 20. watchdog timer on page 77.
HMS81C43XX / gms87c4060 84 november 2001 ver 1.2 23. otp programming 23.1 gms87c4060 otp programming you can burn out gms87c4060 otp through the general gang programmer using intel 27010/c010 mode. in dev- leopment tool package auxiliary, gms87c4060-to-27010/ c010 conversion socket is included. gms87c4060 have two rom memory areas. one is program rom memory and the other is font rom memory. program rom area is from 1000h to ffffh font rom area is from 10000h to 13fffh. when you acquire new otp, actually, the otp is not fully blank. the opt have six test pattern in the osd font rom memory(see figure23-1). the test pattern are written at 11fa0h ~ 11fffh and 13fa0h ~ 13fffh. note: do not write any data in this area(11fa0h ~ 11fffh, 13fa0h ~ 13fffh) blank check if you run blank check function of rom writer, rom writer inform blank error because of test pattern. to avoid this situation, you must run the blank check function sep- eretely. for example, check otp address rage of 1000h ~ 11f9fh at first. and then check opt address range of 12000h ~ 13f9fh. if you have rom writer without partial blank check function, please do not run blank check func- tion. figure 23-1 gms87c4060 otp memory map program writing there are two kind of otp file. one is program otp file(***.otp) and the other is font otp file(***.fnt). you can make each file through asmlinker.exe and osdfont.exe respectively. all otp file is motolora s- format. you can burn the program file and font file respec- tively or together. to burn program file and font file re- spectively, refer following procedure 1. make program otp file and font otp file repec- tively. 2. check whether six test pattern is included in font otp file(see below six text pattern) 3. burn program otp file(set chip target address 1000h ~ ffffh) 4. burn font otp file(set chip target address 10000h ~13fffh) note: when you program the otp file, do not check the blank. because there are already written data(six test pat- tern / 11fa0h ~ 11fffh, 13fa0h~13fffh) it will occur blank error to burn program file and font file together, refer following procedure 1. add program otp file and font otp file 2. check whether six test pattern is included in font otp file(see below six text pattern) 3. burn otp file(set chip target address 1000h ~ 13fffh) about other details, refer rom wirter manual. six test pattern when you make font file through osdfont.exe, please confirm whether six test pattern is included or not in char- acter address 1fah ~ 1ffh, to include six test patern, refer following procedure. 1. make font file and save it to your pc 2. reopen the font file and save it to your hdd once again. 3. then six test pattern will be included automatically. (character address 1fah ~ 1ffh) 1000h ffffh 13fffh osd font memory program memory
HMS81C43XX / gms87c4060 85 november 2001 ver 1.2 23.2 .device configuration data figure 23-2 figure pin configuration in otp programming mode figure 23-3 figure mode table hynix gms87c4060 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a3 a2 a1 a0 o7 o6 o5 o4 o3 a16 a4 a5 gnd ceb pgmb oeb v cc v pp o0 o1 o2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 gms87c4060 intel 27010 mode vpp ceb oeb pgmb vpp ceb oeb pgmb program 12.75v low high *2 low *1 12.75v low high low verify 12.75v low low high 12.75v low low high optional ve r i f y 5v low low x 5v low low x gang write *3 12.75v low high low 12.75v low high low gang verify *4 12.75v, 5v low low x 12.75v low low x
HMS81C43XX / gms87c4060 86 november 2001 ver 1.2 *1: low = input low voltage = v il (<0.8v) *2: high = input high value = vil(>2.0v) *3: in gang write mode, all otps are programmed sim- ulaneously. so all signals of otps are in the same condi- tion *4: in gang verify mode, the vpp pin can be sset to both normal high(5v), aand 12.75v and chip slecection is pos- sible using the ceb pin figure 23-4 figure ac programming characteristics limits symbol parameter min typ max unit conditions tas address setup time 2 m s toes oeb setup time 2 m s tds data setup time 2 m s tah address hold time 0 m s tdh data hold time 2 m s tdfp oeb high to output float delay 0 130 ns note1 tvps vpp setup time 2 m s tces ceb setup time 2 m s tpw pgmb initial program pulse width 95 100 105 m s quick pulse programming toe data valid from oeb 100 ns tacc address to output delay 150 ns toh output hold from addresses ceb or oeb whichever occurrs first 00ns tce ceb to output delay 100 ns tcs chip selection interval (@gang verify) 100 ns *note1: output float is defined as the point where data is no longer driven
HMS81C43XX / gms87c4060 87 november 2001 ver 1.2 figure 23-5 pin mapping table between intel 27010/c010 and gms87c4060 intel 27010 gms87c4060 pin name pin number pin name pin number vpp 1 test_n 38 a16 2 r67 26 a153r271 a124r244 a7 5 r17 9 a6 6 r16 10 a5 7 r15 15 a4 8 r14 16 a3 9 r13 17 a2 10 r12 18 a1 11 r11 19 a0 12 r10 20 o0 13 r00 29 o1 14 r01 28 o2 15 r02 27 gnd 16 vss 12, 40 o3 17 r03 25 o4 18 r04 24 o5 19 r05 23 o6 20 r06 22 o7 21 r07 21 ceb 22 r41 51 a10 23 r22 6 oeb 24 r53 41 a11 25 r23 5 a9 26 r21 7 a8 27 r20 8 a13 28 r25 3 a14 29 r26 2 n.c. 30 pgmb 31 r52 42 vcc 32 vdd 39
HMS81C43XX / gms87c4060 88 november 2001 ver 1.2 figure 23-6 connection of other pins of gms87c4060 in otp mode 23.3 timing chart figure 23-7 figure programming timing chart pin name pin number connect to reset_n 11 gnd xout 13 not connect xin 14 gnd r 30 not connect g 31 not connect b 32 not connect r56 33 not connect r55 34 not connect r54 35 not connect osc2 36 not connect osc1 37 gnd r47 45 gnd r46 46 gnd r45 47 gnd r44 48 gnd r43 49 not connect r42 50 not connect r40 52 gnd r50 44 vdd r51 43 vdd address vpp data in stable ceb data pgmb oeb v ih v il v ih v il 12.5v 5v v ih v il data out valid valid ouput v ih v il v ih v il address stable program verify optinal verify address valid tas tds tdh tvps tah tdfp tces tpw toes toe toe high z dont care dont care dont care
HMS81C43XX / gms87c4060 89 november 2001 ver 1.2 figure 23-8 ac wave form in gang verify mode address oeb data ceb[0] v ih v il v ih v il v ih v il v ih v il address stable optinal verify 0th otp 1st otp data data data ..... tacc (n-1)th otp ceb[1] v ih v il tcs tacc ceb[n-1] v ih v il tacc 1) when you verify the data in the same address of many otps. when you select otps using ceb, and can verify the data inthe same address. (pgmb : dont care , vpp : v ih or 12.5v ) oeb ceb[0] v ih v il v ih v il tacc ceb[1] v ih v il tcs tacc ceb[n-1] v ih v il tacc oeb ceb[0] v ih v il v ih v il tacc addr0 addr2 addr3 addr1 data0 data1 data2 data3 tacc tacc tacc tacc data address v ih v il v ih v il 2) when you verify the data in s single otp throughout the rom address
HMS81C43XX / gms87c4060 90 november 2001 ver 1.2 24. assemble mnemonics 24.1 instruction map 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 nop set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc // // // sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg // // // cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di // // // or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv // // // and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc // // // eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg // // // lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei // // // ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xas 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel // // // sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel // // // cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel // // // or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel // // // and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel // // // eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel // // // lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel // // // sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
HMS81C43XX / gms87c4060 91 november 2001 ver 1.2 24.2 alphabetic order table of instruction no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 10 and #imm 84 2 2 logical and n - - - - - z - 11 and dp 85 2 3 a ? a ^ (m) 12 and dp + x 86 2 4 13 and !abs 87 3 4 14 and !abs+y 95 3 5 15 and [dp+x] 96 2 6 16 and [dp] + y 97 2 6 17 and {x} 94 1 3 18 and1 m.bit 8b 3 4 bit and c-flag : c ? c ^ (m.bit) - - - - - - - c 19 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c ^ ~(m.bit) - - - - - - - c 20 asl a 08 1 2 arithmetic shift left n - - - - - zc 21 asl dp 09 2 4 22 asl dp + x 19 2 5 23 asl !abs 18 3 5 24 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 25 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 26 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 27 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 28 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 29 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 30 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 31 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 32 bit !abs 1c 3 5 z ? a ^ m, n ? (m 7 ), v ? (m 6 ) 33 bmi rel 90 2 2/4 branch if munus : if (n) = 1, then pc ? pc + rel - - - - - - - - 34 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 35 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 36 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 37 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 38 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 39 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel 40 call !abs 3b 3 8 subroutine call - - - - - - - - 41 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) 42 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 43 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 44 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 45 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 46 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 47 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
HMS81C43XX / gms87c4060 92 november 2001 ver 1.2 48 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 49 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 50 cmp dp 45 2 3 a - (m) 51 cmp dp + x 46 2 4 52 cmp !abs 47 3 4 53 cmp !abs + y 55 3 5 54 cmp [dp + x] 56 2 6 55 cmp [dp] + y 57 2 6 56 cmp {x} 54 1 3 57 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 58 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 59 cmpx dp 6c 2 3 x - (m) 60 cmpx !abs 7c 3 4 61 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 62 cmpy dp 8c 2 3 y - (m) 63 cmpy !abs 9c 3 4 64 com dp 2c 2 4 1s complement : (dp) ? ~(dp) n - - - - - z - 65 daa df 1 3 decimal adjust for addition n - - - - - zc 66 das cf 1 3 decimal adjust for substraction n - - - - - zc 67 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 68 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 69 dec a a8 1 2 decrement n - - - - - z - 70 dec dp a9 2 4 m ? m - 1 71 dec dp + x b9 2 5 72 dec !abs b8 3 5 73 dec x af 1 2 74 dec y be 1 2 75 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 76 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 77 div 9b 1 12 divide : ya / x ? q:a, r:y nv - - h - z - 78 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 79 eor #imm a4 2 2 exclusive or n - - - - - z - 80 eor dp a5 2 3 a ? a ? (m) 81 eor dp + x a6 2 4 82 eor !abs a7 3 4 83 eor !abs + y b5 3 5 84 eor [ dp + x] 96 2 6 85 eor [dp] + y 97 2 6 86 eor {x} 94 1 3 87 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 88 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? ~ (m.bit) - - - - - - - c 89 inc a 88 1 2 increment n - - - - - zc 90 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 91 inc dp + x 99 2 5 92 inc !abs 98 3 5 93 inc x 8f 1 2 94 inc y 9e 1 2 95 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z - 96 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 97 jmp [!abs] 1f 3 5 pc ? jump address 98 jmp [dp] 3f 2 4 no. mnenonic op code byte no. cycle no operation flag nvgbhizc
HMS81C43XX / gms87c4060 93 november 2001 ver 1.2 99 lda #imm c4 2 2 load accumulator n - - - - - z - 100 lda dp c5 2 3 a ? (m) 101 lda dp + x c6 2 4 102 lda !abs c7 3 4 103 lda !abs + y d5 3 5 104 lda [dp + x] d6 2 6 105 lda [dp]+y d7 2 6 106 lda {x} d4 1 3 107 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 108 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 109 ldcb m.bit cb 3 4 load c-flag with not : c ? ~(m.bit) - - - - - - - c 110 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 111 ldx #imm 1e 2 2 load x-register n - - - - - z - 112 ldx dp cc 2 3 x ? (m) 113 ldx dp + y cd 2 4 114 ldx !abs dc 3 4 115 ldy #imm 3e 2 2 load x-register n - - - - - z - 116 ldy dp c9 2 3 y ? (m) 117 ldy dp + y d9 2 4 118 ldy !abs d8 3 4 119 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 120 lsr a 48 1 2 logical shift right n - - - - - zc 121 lsr dp 49 2 4 122 lsr dp + x 59 2 5 123 lsr !abs 58 3 5 124 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 125 nop 00,ff 1 2 no operation - - - - - - - - 126 not1 m.bit 4b 3 5 bit complement : (m.bit) ? ~(m.bit) - - - - - - - - 127 or #imm 64 2 2 logical or n - - - - - z - 128 or dp 65 2 3 a ? a v (m) 129 or dp + x 66 2 4 130 or !abs 67 3 4 131 or !abs + y 75 3 5 132 or [dp +x} 76 2 6 133 or [dp] + y 77 2 6 134 or {x} 74 1 3 135 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 136 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v ~(m.bit) - - - - - - - c 137 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " 138 pop a 0d 1 4 pop from stack - - - - - - - - 139 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 140 pop y 4d 1 4 141 pop psw 6d 1 4 (restored) 142 push a 0e 1 4 push to stack - - - - - - - - 143 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 144 push y 4e 1 4 145 push psw 6e 1 4 146 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 147 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp) no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ?
HMS81C43XX / gms87c4060 94 november 2001 ver 1.2 148 rol a 28 1 2 rotate left through carry n - - - - - zc 149 rol dp 29 2 4 150 rol dp + x 39 2 5 151 rol !abs 38 3 5 152 ror a 68 1 2 rotate right through carry n - - - - - zc 153 ror dp 69 2 4 154 ror dp + x 79 2 5 155 ror !abs 78 3 5 156 sbc #imm 24 2 2 substract with carry nv - - hzc 157 sbc dp 25 2 3 a ? a - (m) - ~(c) 158 sbc dp + x 26 2 4 159 sbc !abs 27 3 4 160 sbc !abs + y 35 3 5 161 sbc [dp + x] 36 2 6 162 sbc [dp] + y 37 2 6 163 sbc {x} 34 1 3 164 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 165 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 166 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 167 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 168 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 169 sta dp + x e6 2 4 (m) ? a 170 sta !abs e7 3 4 171 sta !abs + y f5 3 5 172 sta [dp + x] f6 2 6 173 sta [dp] + y f7 2 6 174 sta {x} f4 1 3 175 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 176 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 177 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 178 stx dp + y ed 2 5 (m) ? x 179 stx !abs fc 3 5 180 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 181 sty dp + x f9 2 5 (m) ? y 182 sty !abs f8 3 5 183 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 184 subw dp 3d 2 5 16-bits substract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc 185 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 186 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 187 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h) 188 tclr1 !abs 5c 3 6 test and clear bits with a : n - - - - - z - a - (m), (m) ? (m) ^ ~(a) 189 tset1 !abs 3c 3 6 test and set bits with a : n - - - - - z - a - (m), (m) ? (m) v (a) 190 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 191 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 192 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 193 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 194 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 195 xax ee 1 4 exchange x-register contents with accumulator : x f a - - - - - - - - 196 xay de 1 4 exchange y-register contents with accumulator : y f a - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
HMS81C43XX / gms87c4060 95 november 2001 ver 1.2 24.3 instruction table by function 1. arithmetic/logic operation 197 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 f a 3 ~ a 0 198 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 199 xma dp + x ad 2 6 (m) f a 200 xma {x} bb 1 5 201 xyx fe 1 4 exchange x-register contents with y-register : x f y - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 and #imm 84 2 2 logical and n - - - - - z - 10 and dp 85 2 3 a ? a ^ (m) 11 and dp + x 86 2 4 12 and !abs 87 3 4 13 and !abs+y 95 3 5 14 and [dp+x] 96 2 6 15 and [dp] + y 97 2 6 16 and {x} 94 1 3 17 asl a 08 1 2 arithmetic shift left n - - - - - zc 18 asl dp 09 2 4 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 22 cmp dp 45 2 3 a - (m) 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 25 cmp !abs + y 55 3 5 26 cmp [dp + x] 56 2 6 27 cmp [dp] + y 57 2 6 28 cmp {x} 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 30 cmpx dp 6c 2 3 x - (m) 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 33 cmpy dp 8c 2 3 y - (m) 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : (dp) ? ~(dp) n - - - - - z - 36 daa df 1 3 decimal adjust for addition n - - - - - zc 37 das cf 1 3 decimal adjust for substraction n - - - - - zc 38 dec a a8 1 2 decrement n - - - - - z - 39 dec dp a9 2 4 m ? m - 1 40 dec dp + x b9 2 5 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
HMS81C43XX / gms87c4060 96 november 2001 ver 1.2 44 div 9b 1 12 divide : ya / x ? q:a, r:y nv - - h - z - 45 eor #imm a4 2 2 exclusive or n - - - - - z - 46 eor dp a5 2 3 a ? a ? (m) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 49 eor !abs + y b5 3 5 50 eor [ dp + x] 96 2 6 51 eor [dp] + y 97 2 6 52 eor {x} 94 1 3 53 inc a 88 1 2 increment n - - - - - zc 54 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 55 inc dp + x 99 2 5 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 logical shift right n - - - - - zc 60 lsr dp 49 2 4 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 64 or #imm 64 2 2 logical or n - - - - - z - 65 or dp 65 2 3 a ? a v (m) 66 or dp + x 66 2 4 67 or !abs 67 3 4 68 or !abs + y 75 3 5 69 or [dp +x} 76 2 6 70 or [dp] + y 77 2 6 71 or {x} 74 1 3 72 rol a 28 1 2 rotate left through carry n - - - - - zc 73 rol dp 29 2 4 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry n - - - - - zc 77 ror dp 69 2 4 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 substract with carry nv - - hzc 81 sbc dp 25 2 3 a ? a - (m) - ~(c) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 84 sbc !abs + y 35 3 5 85 sbc [dp + x] 36 2 6 86 sbc [dp] + y 37 2 6 87 sbc {x} 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 89 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 f a 3 ~ a 0 no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ? c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
HMS81C43XX / gms87c4060 97 november 2001 ver 1.2 2. register / memory operation 3. 16-bit operation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator n - - - - - z - 2 lda dp c5 2 3 a ? (m) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 6 lda [dp + x] d6 2 6 7 lda [dp]+y d7 2 6 8 lda {x} d4 1 3 9 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 11 ldx #imm 1e 2 2 load x-register n - - - - - z - 12 ldx dp cc 2 3 x ? (m) 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load x-register n - - - - - z - 16 ldy dp c9 2 3 y ? (m) 17 ldy dp + y d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 20 sta dp + x e6 2 4 (m) ? a 21 sta !abs e7 3 4 22 sta !abs + y f5 3 5 23 sta [dp + x] f6 2 6 24 sta [dp] + y f7 2 6 25 sta {x} f4 1 3 26 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 28 stx dp + y ed 2 5 (m) ? x 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 31 sty dp + x f9 2 5 (m) ? y 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 36 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 37 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 38 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 39 xax ee 1 4 exchange x-register contents with accumulator : x f a - - - - - - - - 40 xay de 1 4 exchange y-register contents with accumulator : y f a - - - - - - - - 41 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 42 xma dp + x ad 2 6 (m) f a 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x f y - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 3 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 4 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z -
HMS81C43XX / gms87c4060 98 november 2001 ver 1.2 4. bit manipulation 5. branch / jump operation 5 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 6 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 7 subw dp 3d 2 5 16-bits substract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? c ^ (m.bit) - - - - - - - c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c ^ ~(m.bit) - - - - - - - c 3 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 4 bit !abs 1c 3 5 z ? a ^ m, n ? (m 7 ), v ? (m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 6 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 7 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 8 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - 9 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? ~ (m.bit) - - - - - - - c 12 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~(m.bit) - - - - - - - c 14 not1 m.bit 4b 3 5 bit complement : (m.bit) ? ~(m.bit) - - - - - - - - 15 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v ~(m.bit) - - - - - - - c 17 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 18 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 19 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 20 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 21 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 22 tclr1 !abs 5c 3 6 test and clear bits with a : n - - - - - z - a - (m), (m) ? (m) ^ ~(a) 23 tset1 !abs 3c 3 6 test and set bits with a : n - - - - - z - a - (m), (m) ? (m) v (a) no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 2 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 4 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 5 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 6 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 7 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 8 bmi rel 90 2 2/4 branch if munus : if (n) = 1, then pc ? pc + rel - - - - - - - - 9 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 10 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 11 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 12 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 13 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel
HMS81C43XX / gms87c4060 99 november 2001 ver 1.2 6. control operation & etc. 14 call !abs 3b 3 8 subroutine call - - - - - - - - 15 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) 16 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 17 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 19 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 20 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 21 jmp [!abs] 1f 3 5 pc ? jump address 22 jmp [dp] 3f 2 4 23 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " 24 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h) no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 2 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 3 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 4 nop ff 1 2 no operation - - - - - - - - 5 pop a 0d 1 4 pop from stack - - - - - - - - 6 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 7 pop y 4d 1 4 8 pop psw 6d 1 4 (restored) 9 push a 0e 1 4 push to stack - - - - - - - - 10 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 11 push y 4e 1 4 12 push psw 6e 1 4 13 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 14 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp)
HMS81C43XX / gms87c4060 100 november 2001 ver 1.2

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